Texas Instruments ADS7881 User Manual Download Page 2

1 Introduction

The ADS78x1EVM showcases the 12-bit, 4-MSPS (ADS7881) and 14-bit, 3-MSPS (ADS7891) ADCs. The 
ADS7881 and ADS7891 devices include a capacitor-based successive-approximation register (SAR) ADC with 
inherent sample and hold. These devices offer either a 12-bit or 14-bit parallel interface. Both devices offer byte 
mode operation that enables easy interface with 8-bit processors. They also have a pseudo-differential input 
stage and a 2.5-V internal reference.

This evaluation module serves as a reference design and a low-cost method to test these converters in the end 
application. The following sections describe the pin outs of the various analog, power, and digital connectors and 
power requirements.

Table 1-1

 lists documents related to the ADS78x1EVM.

Table 1-1. Related Documentation from Texas Instruments

Data Sheets

Literature Number

ADS7881

SLAS400

ADS7891

SLAS410

ADS8411

SLAS369

THS4031

SLOS224

OPA132

SBOS054

REF1004-2.5

SBVS032

SN74AHC138

SCLS258

SN74AHC245

SCLS230

SN74AHC1G04

SCLS318

1.1 Features

The ADS78x1EVM includes the following features:

• Full-featured evaluation board for the high-speed, SAR-type ADS7881(12-bit, 4-MSPS) or ADS7891(14-bit, 

3-MSPS) single-channel, parallel interface ADCs

• Onboard signal conditioning
• Onboard reference
• Input and output digital buffers
• Onboard decoding for stacking multiple EVMs

1.2 Analog Interface

The ADS7881 and ADS7891 ADCs have both a positive and negative analog input pin. The negative input pin, 
which has a range of –200 mV up to 200 mV is shorted on the board. A signal for the positive input pin can be 
applied at connector P1, pin 2 (as shown in 

Table 1-2

) or at the center pin of the SMA connector J2.

Table 1-2. Analog Input Connector

Connector.Pin#

(1)

Signal

Description

P1.2

+IN

Noninverting input channel

P1.4

Reserved

P1.6

Reserved

P1.8

Reserved

P1.10

Reserved

P1.12

Reserved

P1.14

Reserved

P1.16

Reserved

P1.18

Reserved

P1.20

REF+

External reference input

(1)

All odd-numbered pins of P1 are tied to AGND.

Introduction

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2

ADS7881EVM, ADS7891EVM Evaluation Module

SLAU150A – DECEMBER 2004 – REVISED OCTOBER 2021

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Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for ADS7881

Page 1: ...2 1 Decoding Control Signals Using the Address Bus 7 Figure 4 1 Top Layer Layer 1 10 Figure 4 2 Ground Plane Layer 2 11 Figure 4 3 Power Plane Layer 3 12 Figure 4 4 Bottom Layer Layer 4 13 Figure 5 1...

Page 2: ...SCLS230 SN74AHC1G04 SCLS318 1 1 Features The ADS78x1EVM includes the following features Full featured evaluation board for the high speed SAR type ADS7881 12 bit 4 MSPS or ADS7891 14 bit 3 MSPS single...

Page 3: ...al but also isolates the amplifier from the capacitive load The capacitor to ground at the input of the ADC works in conjunction with the series resistor to filter the input signal and functions as a...

Page 4: ...U2 to ground Installed Short to pin 4 of amplifier U2 to VCC Installed 1 1 Factory set condition 1 3 Digital Interface The ADS78x1EVM is designed for easy interfacing to multiple platforms Samtec part...

Page 5: ...EVM to a host processor Table 1 6 Data Bus Connector P3 Connector Pin 1 Signal Name Description ADS7881 ADS7891 P3 1 B_DB0 Not connected Buffered data bit 0 LSB P3 3 B_DB1 Not connected Buffered data...

Page 6: ...digital section of the board ADC address decoder buffers There are two ways to provide these voltages 1 Wire in voltages as listed in Table 1 8 at test points on the EVM Table 1 8 Power Supply Test P...

Page 7: ...be applied via test point TP12 or connector J1 pin 1 As a software test platform connectors P1 P2 and P3 plug into the parallel interface connectors of the 5 6K interface card The 5 6K interface card...

Page 8: ...ternate C1608C0G1H102J CAP CER 1000 pF 50V C0G 5 0603 17 13 0 01 F C4 C10 C13 C20 C21C26 C41 C44 C46 C48 C50 C53 C56 603 TDK Corporation or Alternate C1608X7R1H103KT CAP CER 10000 pF 50V X7R 10 0603 1...

Page 9: ...c SSW 105 22 S D VS 0 025 SMT socket bottom side of PWB 43 1 Samtec TSM 105 01 T D V P 0 025 SMT plug top side of PWB 44 1 SMA_PCB_MT J2 SMA_JACK Johnson Components Inc 142 0701 301 Right angle SMA co...

Page 10: ...te the silkscreens for the ADS78x1EVM Figure 4 1 Top Layer Layer 1 ADS78x1EVM Layout www ti com 10 ADS7881EVM ADS7891EVM Evaluation Module SLAU150A DECEMBER 2004 REVISED OCTOBER 2021 Submit Document F...

Page 11: ...2 Ground Plane Layer 2 www ti com ADS78x1EVM Layout SLAU150A DECEMBER 2004 REVISED OCTOBER 2021 Submit Document Feedback ADS7881EVM ADS7891EVM Evaluation Module 11 Copyright 2021 Texas Instruments Inc...

Page 12: ...3 Power Plane Layer 3 ADS78x1EVM Layout www ti com 12 ADS7881EVM ADS7891EVM Evaluation Module SLAU150A DECEMBER 2004 REVISED OCTOBER 2021 Submit Document Feedback Copyright 2021 Texas Instruments Inco...

Page 13: ...4 Bottom Layer Layer 4 www ti com ADS78x1EVM Layout SLAU150A DECEMBER 2004 REVISED OCTOBER 2021 Submit Document Feedback ADS7881EVM ADS7891EVM Evaluation Module 13 Copyright 2021 Texas Instruments Inc...

Page 14: ...B_DB0 B_DB1 B_DB2 B_DB3 B_DB4 B_DB5 B_DB6 B_DB7 B_DB8 B_DB9 B_DB10 B_DB11 B_DB12 B_DB13 AVCC BVDD 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20...

Page 15: ...1 2 SJP7 3 1 2 SJP6 3 2 6 7 4 5 1 8 U2 THS4031 C30 NI TP9 R1 21 R2 NI REFIN 1 REFOUT 2 NC 3 VA 4 AGND 5 IN 6 IN 7 AGND 8 VA 9 VA 10 AGND 11 AGND 12 AGND 14 AGND 15 DB13 16 DB12 17 DB11 18 DB10 19 DB9...

Page 16: ...DB7 B_DB4 B_DB6 B_DB5 CS RD CONVST BYTE PWN RST B_BUSY 1 16 2 15 3 14 4 13 5 9 12 6 8 10 11 7 RP2 100 OE DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 VCC GND U5 SN74AHC245PWR VBD C25 0 1uF CS R...

Page 17: ...91EVM to ADS78x1EVM throughout document 1 Added Related Documentation from Texas Instruments table to Introduction section 2 Changed paragraph preceding Data Bus Connector P3 4 Changed Data Bus Connec...

Page 18: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 19: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 20: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 21: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 22: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 23: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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