Texas Instruments ADS58J64 EVM, User Manual, Page: 11 / 20

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Optimizing Evaluation Results
11 SBAU284 – January 2017
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ADS58J64 EVM
3.2 LMK04828 Clocking Configuration
The sampling clock provided to the ADS58J64 device is generated by the LMK04828 device in the default
EVM hardware configuration. Configuration scripts are provided with the Configuration GUI to set up the
LMK04828 device in two different states, as shown in
Table 4 .
The states use the full PLL1 + PLL2 operation and use the onboard VCXO (Y1) for PLL1. If it is required
to operate the LMK04828 device in clock distribution mode, the onboard VCXO must be disabled by
removing the shorting jumper at JP2.
Table 4. LK04828 Macro States Provided in Configuration GUI
Macro State Script LMK04828 Mode
ADS58J64 Device
Clock Frequency
Clock Frequency
Required at
LMK_CLK_IN (J12)
Configuration GUI
Shortcut
JP2
LMK04828_config2_737M.cfg PLL1 + PLL2 737.26 MHz 61.44 MHz Button on INTRO tab Short
LMK04828_config2_983M.cfg PLL1 + PLL2 983.04 MHz 61.44 MHz Button on INTRO tab Short
LMK04828_config1.cfg Clock distribution Equal to frequency
at LMK_CLK_IN Flexible not available Open
3.3 Using an External Clock
The LMK04828 device provides a very low-noise device clock, but the noise performance may not be as
good as a premium bench RF signal generator, so the measured noise performance of the ADS58J64
device can be optimized by using an external signal generator as a clock source.
To provide the ADS58J64 device with an external clock (through EXT_ADC_CLK, J6 on the EVM), the
following hardware changes must be performed on the EVM:
• Remove C47 and C48
• Place R35 and R39 with 0.1-µF 0402 capacitors.
The external clock is provided to the EVM through the J6 SMA connector at the full device clock rate
(983.04 or 737.26 MHz), and amplitude of 6 dBm. This signal path must be filtered to reduce the
broadband noise and remove any nonharmonic spurs. Narrow-band filters are recommended to remove
as much noise as possible. If a signal generator output is used directly without filtering, significant
degradation in SNR results.
A signal with the same frequency must also be provided to the LMK_CLK_IN J12 SMA connector with an
amplitude of 6 dBm. If these signals are provided from different signal generators, the frequencies of the
signals provided to J6 and J12 must be frequency locked together. Alternatively, a power splitter may be
used to divide the signal from a single clock generator. When using an external clock, the LMK04828
device must be configured using the
LMK04828_config1.cfg macro.