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ADS5102/3 EVM Operational Procedure

1-3

Overview

1.4

ADS5102/3 EVM Operational Procedure

The ADS5102/3 EVM provides a flexible means of evaluating the ADS5102/3
in a number of modes of operation. A basic setup procedure that can be used
as a board confidence check is as follows:

1) Verify all jumper settings against the schematic jumper list in Table 1–1

and Table 1–2:

Table 1–1. Two Pin Jumper List

Jumper

Function

Installed

Removed

Default

W10

External REFT feed

External

Internal

Removed

W11

External REFB feed

External

Internal

Removed

R39

Positive analog input

Transformer coupled

No connection

Installed

R37

Negative analog input

Transformer coupled

No connection

Installed

R38

Positive analog input

Differential amplifier

No connection

Removed

R36

Negative analog input

Differential amplifier

No connection

Removed

R43, R44

Output clock option

ADC clock at output connector

Buff clock at output
connector

Removed

R42

Optional output clock
parallel termination

Provides pullup termination

No pullup termination

Removed

R14

Optional ADC clock
parallel termination

Provides pullup termination

No pullup termination

Removed

Table 1–2. Three Pin Jumper List

Jumper

Function

Location: Pins 1–2

Location: Pins 2–3

Default

W1

Band gap input voltage
(power down reference
mode)

REFT voltage to bandgap pin

1.25 V to bandgap pin

Removed

W3

Transformer and diff amp
common mode select

ADC output common mode
voltage

External common
mode voltage

1–2

W4

Power down select

Operate mode

Power down mode

1–2

W5

Output enable select

Data bus tristate

Data bus enable

2–3

W6

Reference select

External reference

Internal reference

2–3

2) Connect supplies to the EVM as follows:

J

1.8-V analog supply to J6 and return to J5

J

1.8-V digital supply to J9 and return to J10

J

3.3-V driver supply to J13 and return to J14

J

5-V analog supply to J7 and return to J8

J

–5-V analog supply to J11 and return to J8

Summary of Contents for ADS5102 EVM

Page 1: ...ADS5102 3 EVM December 2001 AAP High Speed Data Converter Dallas User s Guide SLAU077 ...

Page 2: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

Page 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Page 4: ... there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is designed to operate properly with certain components above 60 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistor...

Page 5: ... Chapter 3 Circuit Description Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in ...

Page 6: ...h the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference ...

Page 7: ... 2 1 PCB Layout 2 2 2 2 Bill of Materials 2 5 3 Circuit Description 3 1 3 1 Circuit Function 3 2 3 1 1 Analog Inputs 3 2 3 1 2 External Reference Inputs 3 2 3 1 3 Clock Inputs 3 3 3 1 4 Control Inputs 3 3 3 1 5 Power 3 3 3 1 6 Outputs 3 3 3 2 Schematic Diagram 3 4 Figures 2 1 Top Layer 2 2 2 2 Inner Layer 1 Ground Plane 2 3 2 3 Inner Layer 2 Power Plane 2 4 2 4 Bottom Layer 2 5 ...

Page 8: ...ii Tables 1 1 Two Pin Jumper List 1 3 1 2 Three Pin Jumper List 1 3 2 1 Bill of Materials 2 5 3 1 Reference Voltage Adjustment Ranges 3 2 3 2 Output Connector J15 3 4 Notes Cautions and Warnings Voltage Limits 1 2 ...

Page 9: ...ADS5102 3 evaluation module EVM and provides a general description of the features and functions to be considered while using this module Topic Page 1 1 Purpose 1 2 1 2 EVM Basic Functions 1 2 1 3 Power Requirements 1 2 1 4 ADS5102 3 EVM Operational Procedure 1 3 Chapter 1 ...

Page 10: ... buffered before going to this connector More information on this connector can be found in the ADC output section Power connections to the EVM are via banana jack sockets Separate sockets are provided for the analog and digital supply In addition to the internal reference provided by the ADS5102 3 device options are provided on the EVM to allow adjustment of the ADC references via an onboard refe...

Page 11: ... option ADC clock at output connector Buff clock at output connector Removed R42 Optional output clock parallel termination Provides pullup termination No pullup termination Removed R14 Optional ADC clock parallel termination Provides pullup termination No pullup termination Removed Table 1 2 Three Pin Jumper List Jumper Function Location Pins 1 2 Location Pins 2 3 Default W1 Band gap input voltag...

Page 12: ... generator with 50 Ω output to input a 1 5 V offset 3 V p p amplitude square wave signal into J4 to be used as the buffered output clock Note This signal must be the same frequency and synchronized with the ADC clock 6 Use a frequency generator with 50 Ω output to input a 1 5 MHz 0 V offset 0 4 V p p amplitude sine wave signal into J2 This provides a transformer coupled differential signal to the ...

Page 13: ...cription Physical Description This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module Topic Page 2 1 PCB Layout 2 2 2 2 Bill of Materials 2 5 Chapter 2 ...

Page 14: ...2 2 1 PCB Layout The EVM is constructed on a 4 layer 104 mm 4 1 inch x 114 mm 4 5 inch x 1 57 mm 0 062 inch thick PCB using FR 4 material Figure 2 1 through Figure 2 4 show the individual layers Figure 2 1 Top Layer ...

Page 15: ...PCB Layout 2 3 Physical Description Figure 2 2 Inner Layer 1 Ground Plane ...

Page 16: ...PCB Layout 2 4 Figure 2 3 Inner Layer 2 Power Plane ...

Page 17: ...ntalum 10 10 V 5 10TPA47M SANYO C72 C76 0 1 µF 16 V 10 capacitor 31 ECJ 1VB1C104K Panasonic C12 C37 C62 C66 10 µF 10 V 10 capacitor 9 GRM42X5R106K10 Murata C51 C54 C67 C71 0 01 µF 50 V 10 capacitor 4 AVX C47 C49 C60 1 0 µF 10 V 10 capacitor 10 AVX C40 C46 C58 C59 C77 22 pF 50 V 5 capacitor 2 06035A220JAT2A AVX C38 C39 0 001 µF 16 V 10 capacitor 1 C50 0 047 µF 16 V 10 capacitor 3 C55 C57 1 8 pF 16 ...

Page 18: ...esistor 1 16 W 1 1 Panasonic R46 100 kΩ resistor 1 16 W 1 1 P100KHCT ND Panasonic R47 3 01 kΩ resistor 1 16 W 1 1 Panasonic R45 9 53 kΩ resistor 1 16 W 1 1 ERJ 6GEY0R00V Panasonic R51 1K Pot 3 3296Y 102 Bourns R27 R29 Transformer 1 T1 1T KK81 Mini Circuits T1 SMA connectors 4 2262 0000 09 Macom J1 J4 Black test point 3 5011K Keystone TP9 TP11 Red test point 8 5000K Keystone TP1 TP8 2POS_header 2 T...

Page 19: ...3 1 Circuit Description Circuit Description This chapter describes the circuit function and shows the schematic for the EVM Topic Page 3 1 Circuit Function 3 2 3 2 Schematic Diagram 3 4 Chapter 3 ...

Page 20: ...eing able to use the internal reference of the ADC a reference circuit has been included on the EVM This circuit uses a precision 2 5 V low noise linear regulator as the primary source and allows adjustment of the REFT and REFB signals to the ADC using potentiometers R27 and R28 respectively A third source CML is also generated to provide an adjustable common mode voltage to be used by the transfo...

Page 21: ...ween pins 2 and 3 the ADC is in power down mode The device is in operate mode with jumper W4 installed between pin 1 and pin 2 3 1 4 2 Output Enable With jumper W5 installed between pins 1 and 2 the ADC data outputs are in a 3 state mode The data outputs are enabled with jumper W5 installed between pins 2 and 3 3 1 4 3 Power Down Reference With jumper W6 installed between pins 1 and 2 the ADC inte...

Page 22: ...4 GND 5 NC 25 Data Bit 4 6 GND 26 GND 7 NC 27 Data Bit 3 8 GND 28 GND 9 NC 29 Data Bit 2 10 GND 30 GND 11 NC 31 Data Bit 1 12 GND 32 GND 13 NC 33 Data Bit 0 MSB 14 GND 34 GND 15 Data Bit 9 MSB 35 NC 16 GND 36 GND 17 Data Bit 8 37 NC 18 GND 38 GND 19 Data Bit 7 39 NC 20 GND 40 GND 3 2 Schematic Diagram The following figures show the schematic diagram for the EVM ...

Page 23: ...K81_XFMR 1 2 3 4 5 J2 AIN C15 0 1 uF R13 49 9 C4 470 pF C3 470 pF C12 0 1 uF C38 22 pF C5 470 pF C18 0 1 uF R9 499 R12 523 R1 49 9 1 2 3 4 5 J1 AIN R11 499 R2 49 9 R3 49 9 5VA R10 499 5VA 5 4 8 1 2 VOCM VOUT VOUT 3 6 VCC VCC 7 PD U1 THS4141 C47 0 01 uF C16 0 1 uF C17 0 1 uF C50 0 001 uF C1 1 8 pF C2 1 8 pF C39 22 pF 1 3 2 W3 EXTERNAL_CML EXTERNAL_CML R38 0 R39 0 R37 0 R36 0 R40 0 R43 0 ADC_CLK ADC...

Page 24: ...1 C48 0 01 uF C58 1 uF REFT REFT R19 10K R24 475 R25 953 C49 0 01 uF C59 1 uF REFB C26 0 1 uF C7 470 pF 5VA EXTERNAL_CML REFB EXTERNAL_CML 2 3 1 4 11 U3A OPA4227UA 10 9 8 U3C OPA4227UA 5 6 7 U3B OPA4227UA TP1 TP2 C51 10 uF C52 10 uF 1 2 3 R28 1k C53 10 uF R31 100 C56 0 047 uF R6 49 9 R34 2 0 K 0 1 0 1 C28 0 1 uF R20 10K R26 475 1 2 3 R29 1k C54 10 uF R32 100 C57 0 047 uF R7 49 9 R35 2 0 K 0 1 12 1...

Page 25: ... 5VA Analog Supply 5volts for Ext Components C32 0 1 uF 5VA 1 8VA PS 1 8VD PS 1 8V 3 3VD PS 5VA PS 5VA PS ADS5102 A 3 4 J6 BANANA_JACK J5 BANANA_JACK FB1 FB3 FB5 FB4 FB2 TP4 TP5 TP7 TP8 TP6 J9 BANANA_JACK J10 BANANA_JACK J11 BANANA_JACK J8 BANANA_JACK J7 BANANA_JACK J13 BANANA_JACK J14 BANANA_JACK C67 10 uF C72 47 uF C69 10 uF C71 10 uF C68 10 uF C70 10 uF C74 47 uF C76 47 uF C73 47 uF C75 47 uF C...

Page 26: ...2 14 3Y3 16 3Y4 17 4Y1 19 4Y2 20 4Y3 22 4Y4 23 GND 10 GND 15 GND 21 GND 28 GND 34 GND 39 GND 45 VCC 18 VCC 31 VCC 42 U6 SN74AVC16244DGG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J15 40PIN_IDC ADS5102 A 4 4 C35 0 1 uF C36 0 1 uF C34 0 1 uF DRVDD D9 D8 D7 D6 D0 D1 D2 D3 D4 D5 NC_D00 NC_D01 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 NC_D00 NC_D0...

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