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Texas Instruments ADS1x48EVM User Manual Download Page 40

Figure 5-6. Bottom Layer

Figure 5-7. Bottom Silkscreen

Bill of Materials, Printed Circuit Board Layout, and Schematic

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40

ADS1x48EVM Evaluation Module

SBAU378A – SEPTEMBER 2021 – REVISED JANUARY 2022

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Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for ADS1x48EVM

Page 1: ...nto the ADS1x48 devices enable precision measurement for many types of analog temperature sensors including thermocouples resistance temperature detectors RTDs and thermistors This user s guide descri...

Page 2: ...ut Connections 12 4 ADS1x48EVM GUI 28 4 1 Home 28 4 2 Data Capture 31 4 3 Register Map 33 5 Bill of Materials Printed Circuit Board Layout and Schematic 36 5 1 Bill of Materials 36 5 2 Printed Circuit...

Page 3: ...IDAC and a High Side RREF 22 Figure 3 17 Connection Diagram for a 3 Wire RTD Using Two IDACs and a Low Side RREF 23 Figure 3 18 Connection Diagram for a 3 Wire RTD Using Two IDACs and a High Side RREF...

Page 4: ...nal Block J6 to ADC Connections 17 Table 3 5 ADS1x48EVM Settings for Different RTD Types 26 Table 5 1 Bill of Materials 36 Trademarks Firefox is a trademark of Mozilla Foundation Chrome is a trademark...

Page 5: ...d listed in Table 3 2 The combined ADS1x48EVM and PAMBoard incorporate the following features ADS1x48 a 16 or 24 bit delta sigma ADC with eight input channels Input terminal block and jumper configura...

Page 6: ...rd directly to a USB port on the computer Do not connect the cable through a USB hub 5 Open up the web based GUI available on the EVM landing page ADS1148EVM PDK or ADS1248EVM PDK a First time users m...

Page 7: ...gulator uses this 5 5 V output to provide clean and stable 5 V and 3 3 V supplies from the PAMBoard to the ADS1x48EVM Two LEDs light up on the PAMBoard as shown in Figure 3 1 when the USB cable is plu...

Page 8: ...accept a digital supply voltage DVDD range from 2 7 V to 5 25 V On the ADS1x48EVM the ADS1x48 DVDD is a fixed value of 3 3 V As with AVDD this 3 3 V DVDD is sourced from the USB power supply voltage...

Page 9: ...aximum flexibility Table 3 1 details these four options Figure 3 3 shows the location of each VREF option highlighted in yellow as well as each VREF test point highlighted in red Table 3 1 Summary of...

Page 10: ...his pin is marked GND on the ADS1x48EVM silkscreen Enable an external clock by connecting the shunt to the JP2 1 pin on the JP2 header This pin is marked EXT_CLK on the ADS1x48EVM silkscreen When the...

Page 11: ...2 Use these connection points for troubleshooting the SPI communication with a logic analyzer or to attach an external MCU to control the ADS1x48EVM without the PAMBoard Figure 3 5 ADS1x48EVM to PAMBo...

Page 12: ...rminal Block Input Description J5 and J6 Terminal Block Input Label Description J5 1 TC Positive thermocouple general purpose input J5 2 TC Negative thermocouple general purpose input J5 3 REF5025 2 5...

Page 13: ...e DNP and therefore do not come installed on the EVM To use the pullup and pulldown resistor method install 1 M to 10 M resistors in the aforementioned locations With these resistors installed the the...

Page 14: ...n report This document also discusses the need for cold junction compensation CJC which is used in conjunction with the thermocouple voltage to derive the measured temperature The ADS1x48EVM includes...

Page 15: ...shows two DNP components a thermistor RT1 and a 10 k linearization resistor R14 RT1 can be used for CJC for thermocouple measurements see Section 3 5 2 1 R14 helps linearize the thermistor output volt...

Page 16: ...more accurate thermocouple measurement Figure 3 11 PCB Layout for J5 Terminal Block Showing Copper Pours for CJC Measurement As discussed in Section 3 5 2 and in Figure 3 9 thermistor RT1 is not popu...

Page 17: ..._C 0 01uF C5 1000pF C2 1000pF C6 4 12k R10 4 12k R12 4 02k R11 GND GND GND 1 2 3 4 5 6 J6 GND GND JP3 JP4 JP5 JP6 Figure 3 12 RTD Input Structure on the ADS1x48EVM Table 3 4 ADS1x48EVM Terminal Block...

Page 18: ...ns can be measured with the ADS1x48EVM including 2 wire RTD using a low side RREF 2 wire RTD using a high side RREF 3 wire RTD using one IDAC and a low side RREF 3 wire RTD using one IDAC and a high s...

Page 19: ...Figure 3 13 also shows that for this RTD configuration the RTD is connected to REFP1 and RTD_B Additionally jumpers JP3 and JP4 are connected whereas jumpers JP5 and JP6 are disconnected Finally the...

Page 20: ...14 also shows that for this RTD configuration the RTD is connected to REFN1 and RTD_B Additionally jumpers JP4 JP5 and JP6 are connected whereas jumper JP3 is disconnected Finally the AIN1 pin on the...

Page 21: ...D configuration the RTD is connected to REFP1 RTD_A and RTD_B Additionally jumpers JP3 and JP4 are connected whereas jumpers JP5 and JP6 are disconnected Moreover the IEXC1 current source is enabled F...

Page 22: ...ation the RTD is connected to REFN1 RTD_A and RTD_B Additionally jumpers JP4 JP5 and JP6 are connected whereas jumper JP3 is disconnected Moreover the AIN1 pin on the ADS1x48 is configured to be a cur...

Page 23: ...ow Side RREF Figure 3 17 also shows that for this RTD configuration the RTD is connected to REFP1 RTD_A and RTD_B Additionally jumpers JP3 and JP4 are connected whereas jumpers JP5 and JP6 are disconn...

Page 24: ...ws that for this RTD configuration the RTD is connected to REFN1 RTD_A and RTD_B Additionally jumpers JP4 JP5 and JP6 are connected whereas jumper JP3 is disconnected Finally the AIN1 pin on the ADS1x...

Page 25: ...gure 3 19 also shows that for this RTD configuration the RTD is connected to REFP1 RTD_A RTD_B and RTD_C Additionally jumper JP3 is connected whereas jumpers JP4 JP5 and JP6 are disconnected Finally t...

Page 26: ...on settings 3 5 3 9 Summary of ADS1x48EVM RTD Configuration Settings Table 3 5 summarizes the required IDAC jumper and analog input channel settings to measure each RTD configuration using the ADS1x48...

Page 27: ...on J5 as General Purpose Signal Inputs As Figure 3 21 shows resistors R24 and R23 are not populated by default resulting in a set of analog inputs that are only subject to the differential filter cuto...

Page 28: ...1x48EVM Home Data Capture Register Map The following sections step through each GUI page in more detail 4 1 Home The Home page is the GUI start up landing page The Home page provides a high level over...

Page 29: ...ce name Clicking the icon as shown in Figure 4 3 displays specific information regarding the ADS1x48EVM Figure 4 3 Connected Hardware Information www ti com ADS1x48EVM GUI SBAU378A SEPTEMBER 2021 REVI...

Page 30: ...provides a way to display the current COM port settings in a pop up dialog with options to change the COM port or reconfigure the settings as necessary 4 1 1 3 Tools Menu The Tools drop down menu offe...

Page 31: ...ired input signal amplification SELFOCAL button for performing a device ADC offset calibration Figure 4 6 Capture Settings Slide Out To collect data select the number of Samples to collect in the uppe...

Page 32: ...the standard deviation within the data set Pk to Pk representing the total noise peak to peak within the data set Eff Res representing the effective resolution as number of bits with the value in pare...

Page 33: ...ee dynamic range THD or total harmonic distortion SINAD or signal to noise and distortion ENOB or effective number of bits Harmonics The FFT plot is rather meaningless for dc input voltages However a...

Page 34: ...Bits menu to toggle the bit settings As the bit settings change the Field View options also change to the corresponding register setting 4 3 1 Register Read and Write Options Figure 4 11 highlights th...

Page 35: ...turned off Figure 4 12 Auto Read Options 4 3 1 2 Write Register Options The GUI default option for register writes is Immediate Write When Immediate Write is selected any register configuration change...

Page 36: ...eader 2mm 2x1 Tin TH TMM 102 01 T S Samtec R1 R2 R7 R8 R17 5 RES 10 0 k 1 0 1 W 0603 RC0603FR 0710KL Yageo R3 1 RES 470 5 0 1 W 0603 RC0603JR 07470RL Yageo R4 1 RES 390 1 0 1 W 0603 RC0603FR 07390RL Y...

Page 37: ...bit 2kSPS 8 Ch Delta Sigma ADC for Precision Sensor Measurement PW0028A TSSOP 28 ADS1248IPWR or ADS1148IPWR Texas Instruments R14 0 RES 10 0 k 1 0 1 W 0603 RC0603FR 0710KL Yageo R23 R24 0 RES 10 0 M 1...

Page 38: ...tom layer yellow top silkscreen internal GND layers not shown Figure 5 1 Composite PCB Layout Bill of Materials Printed Circuit Board Layout and Schematic www ti com 38 ADS1x48EVM Evaluation Module SB...

Page 39: ...round Layer 1 Figure 5 5 Internal Ground Layer 2 www ti com Bill of Materials Printed Circuit Board Layout and Schematic SBAU378A SEPTEMBER 2021 REVISED JANUARY 2022 Submit Document Feedback ADS1x48EV...

Page 40: ...ottom Silkscreen Bill of Materials Printed Circuit Board Layout and Schematic www ti com 40 ADS1x48EVM Evaluation Module SBAU378A SEPTEMBER 2021 REVISED JANUARY 2022 Submit Document Feedback Copyright...

Page 41: ...1 2 3 JP2 CLK_EXT CLK_EXT DRDY 0 1 R6 3V3 AVDD GND SCLK EEPROM_WE SCL_LP SDA_LP IEXC1 IEXC2 START 10 0k R7 10 0k R8 10 0M R24 DNP AVDD 10 0M R23 DNP 4 12k R16 4 12k R13 REFOUT 0 01uF C10 0 01uF C12 1...

Page 42: ...22 from Revision September 2021 to Revision A January 2022 Page Deleted inclusive terminology from document 5 Changed EVM landing page links to correct locations throughout document 6 Revision History...

Page 43: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 44: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 45: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 46: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 47: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 48: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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