8.2
Digital Control
8.3
ADS1274EVM-PDK Power Supply
EVM Operation
www.ti.com
The digital control signals can be applied directly to J5 (top or bottom side). The modular ADS1274EVM
can also be connected directly to a DSP or microcontroller interface board, such as the
or
boards available from Texas Instruments, or the MMB0 if purchased as part of
the ADS1274EVM-PDK. For a list of compatible interface and/or accessory boards for the EVM or the
ADS1274, see the relevant product folder on the TI web site. Some of the digital signals are controlled
directly with pins on J5. Other signals such as the Power Down controls can only be controlled with slide
switches or by U17 and U18 that are set up and read using the I
2
C signals on pins 16 and 18 of J5. The
Format and Mode pins can be controlled by all three methods (slide switches, GPIO pins on J5, and the
I
2
C control from U17).
The ADS1274 allows the serial interface to be used in two different formats: an SPI-compatible mode and
a frame-sync format. Switch S12 can be used to switch between these two formats. The left position,
marked
SPI
, selects the SPI format. In this format, the signals are connected in this configuration:
•
The SCLK input of the converter is driven by the serial port signal CLKX, pin J5.3.
•
The signal from the selected source for the clock (see
Clock Source
) is connected to the
CLKR pin (J5.5) allowing the serial port of a processor to be synchronized to the converter master
clock.
•
The signal from the selected clock source is routed to the CLK input of the converter.
•
Port P10 of the I
2
C port expander U18 is connected to a logic high level, so that the position of switch
S12 can be read back by software.
The right position of S12, marked
FS
, selects the frame-sync format. In this format, the signals are
connected in this configuration:
•
The SCLK input of the converter is driven by the serial port signal CLKR, pin J5.5.
•
The signal from the selected clock source is connected to the CLKX pin (J5.3), allowing the serial port
of a processor to be synchronized to the converter master clock.
•
The CLK input of the converter is driven by the CLKR signal (J5.5). This connection ensures that the
CLK and SCLK signals have the same phase and the correct ratio as outlined in the data sheet of the
device.
•
Port P10 of the I
2
C port expander U18 is connected to a logic low level, so that the position of switch
S12 can be read back by software.
For use in the ADS1274EVM-PDK, S12 must be in the right (FS) position, which is the default factory
setting.
Switching to SPI format will allow the EVM to connect to any SPI-compatible processor that does not
support the frame-sync mode. If this format is selected, keep in mind that the high-speed mode will not
work at full speed (32.768MHz) because of the limitations outlined in the device product data sheet.
The ADS1274EVM can either be powered by an AC adapter or by applying the 5V, +10V and –10V to the
connectors on the MMB0 board. The MMB0 board will provide the 5V and 3.3V to the ADS1274EVM
along with the +10V and –10V signals. Because the circuitry is provided on the ADS1274EVM to generate
+10V and –10V, the complete system can be powered from the supplied AC adapter that su6V
and 3A.
ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK
10
SBAU134A – August 2008 – Revised May 2009