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Evaluation Optimization
9
SNAU224 – March 2018
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Copyright © 2018, Texas Instruments Incorporated
ADC117x Evaluation Module
3
Evaluation Optimization
3.1
Clocking Optimization
The sampling clock provided to the ADC needs to have very low phase noise to achieve optimal results.
The default EVM configuration uses a crystal oscillator to generate the sampling clock. Another option to
improve the clock noise performance is bypassing the onboard clock in favor of an external clock. The
clock must have very low noise and must use an external narrow pass-band filter to achieve optimal noise
performance.
3.2
Coherent Input Source
A
Rectangular
window function can be applied to the captured data when the sample rate and the input
frequency are set precisely to capture an integer number of cycles of the input frequency (sometimes
called coherent frequency). This may yield better SNR results. The clock and analog inputs must be
frequency locked (such as through 10-MHz references) in order to achieve coherency.
3.3
HSDC Pro Settings
HSDC Pro has some settings that can help improve the performance measurements. These are
highlighted in
Table 4
.
Table 4. HSDC Pro Settings for Optimizing Results
HSDC Pro Feature
Description
Analysis Window (Samples)
Selects the number of samples to include in the selected test analysis. Collect
more data to improve frequency resolution of Fast-Fourier Transform (FFT)
analysis. If more than 65,536 samples are required, increase the setting in the
Data Capture Options to match this value.
Data Windowing Function
Select the desired windowing function applied to the data for FFT analysis.
Select Blackman when sampling a non-coherent input signal or Rectangle
when sampling a coherent input signal.
Test Options
→
Notch Frequency Bins
Select bins to be removed from the spectrum and back-filled with the average
noise level. May also customize which Harmonics and Spurs are considered
in SNR and THD calculations and select the method for calculating spur
power.
Test Options
→
Bandwidth Integration Markers
Enable markers to narrow the Single-Tone FFT test analysis to a specific
bandwidth.
Data Capture Options
→
Capture Options
Configure the number of contiguous samples per capture (capture depth).
May also enable Continuous Capture and FFT Averaging
4
Alternate Hardware Configurations
This section describes alternate hardware configurations in order to achieve better results or to more
closely mimic the user's system configuration.
4.1
Clocking Options
The default clocking mode uses an onboard oscillator, and clock splitter, to generate the ADC sampling
clock and FPGA clocks.
4.1.1
External Clock
To use an external source to provide the clock signal, shunt JP2 (2-3) and remove the jumper on JP7.
Connect the external clock source to J3.
4.1.2
Clock Splitter Bypass
The clock splitter, U3, receives the clock signal, from the either the onboard oscillator or external source,
and then distributes the clock to the ADC and the FPGA. If desired, the clock splitter signal to the ADC
can be bypassed by shunting JP3 (1-2) and JP5 (1-3).
