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Quick-Start Guide
7
SNAU224 – March 2018
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ADC117x Evaluation Module
ADC1175_cmos
. Select
Yes
when prompted to update the firmware.
4. Once the firmware has been loaded, enter "20M" in the
ADC Output Data Rate
field, and push enter
on the keyboard.
5. Click the
Capture
button. The results of the captured data should look like that of
Figure 5
, and the
performance should be similar to that of
Table 2
.
NOTE:
After performing the capture, ensure that the amplitude of the analog input signal is –1 dBFS
or lower.
Figure 5. ADC1175 Data Capture Using the HSDC Pro GUI
Table 2. Quick-Start Measurements for ADC1175
Result
Measured Value
Units
SNR
46
dBFS
SFDR
53
dBFS
2.2.4
ADC1175-50EVM Setup
See
Section 2.2
if the TSW1400EVM is not set up.
Set up the ADC1175-50EVM using the following steps:
1. Connect the banana jack power-supply cables to the EVM. Connect the red wire to +5 VDC of a power
supply, rated for at least 3 A, and to J4.Connect the black wire to J5 and to GND of the power supply.
2. Turn on the power supply.
3. Ensure JP2 is shunted to the 1-2 position to provide a 20-MHz clock signal to the ADC and CMOS
interface. To use an external clock source, provide an external 20-MHz, 1-dBm, clock signal to J3.
Shunt jumper JP2 to the 2-3 position.
4. Set the analog input signal generator to 5 MHz, +10 dBm.
5. Place a 5-MHz band-pass filter at the output of the analog input signal generator to reduce noise and
harmonics.
