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Tews Technologies TVME8300, User Manual

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Tews Technologies TVME8300 User Manual Download Page 53

 

 

TVME8300 User Manual Issue 1.4 

Page 53 of 70 

8.3 IP 

Interrupts 

The IP FPGA maps all IP interface interrupt sources (Timeout, Error, INT0, INT1) to the PCI9030 local 
interrupt input 1 (LINT1#). The PCI9030 local interrupt 2 (LINT2#) is reserved. 

The PCI9030 PCI Target Chip maps its local interrupt inputs to its PCI interrupt output (INTA#). 

The PCI9030 PCI interrupt output is mapped to the serial interrupt no. 4 of the MPC8245 PIC. 

Upon detecting MPC8245 PIC Serial Interrupt No. 4, read the IP Status Register (PCI9030 Local 
Space 0) to determine the IP interrupt source. 

Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register. 

For using Error interrupts it is assumed that the IP module holds the asserted ERROR# signal level 
and provides an acknowledge mechanism by register access to clear the error signal assertion. If the 
IP module does not hold the asserted ERROR# signal level, there is a possibility of spurious 
interrupts. If the IP module does hold the asserted ERROR# signal level, but does not provide an 
acknowledge mechanism, the ERROR# interrupt should be disabled when entered for the first time. 

 

Summary of Contents for TVME8300

Page 1: ...ual Issue 1 4 September 2006 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany www tews com Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail info tews com 9190 Double Diamond Parkway Suite 127 Reno NV 89521 USA www tews com Phone 1 775 850 5830 Fax 1 775 201 0347 e mail usasales tews com ...

Page 2: ...r TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix 0x i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active L...

Page 3: ...g Frequency corrected January 2004 1 2 Added Installation and Use Notes section Corrected Memory Flash first instruction offset Added Memory Flash Types Updated Technical Information section January 2005 1 3 Ultra 2 SCSI Controller TVME8300 11 Board Option Obsolete June 2006 1 4 New address TEWS LLC September 2006 ...

Page 4: ...p PCI Memory Master View 17 3 3 Address Map PCI I O Master View 18 3 4 Address Map Peripheral Devices Detail 18 3 5 Address Map Utility Register Detail 19 3 5 1 Control Register 19 3 5 2 Status Register 20 3 5 3 Interrupt Register 20 3 5 4 LED Register 21 3 5 5 Jumper Register 21 3 5 6 Fuse Register 22 3 5 7 Utility Register Interrupts 22 4 MPC8245 23 4 1 Configuration Registers 23 4 1 1 Configura...

Page 5: ...1 8 1 3 PCI9030 Configuration EEPROM 42 8 2 IP Interface 44 8 2 1 PCI9030 Local Space Assignment 45 8 2 2 Local Space 0 Address Map 45 8 2 3 IP Interface Register 46 8 2 3 1 Revision ID Register 46 8 2 3 2 IP Control Registers 47 8 2 3 3 Reset Register 48 8 2 3 4 Status Register 49 8 2 4 Local Space 1 Address Map 51 8 2 5 Local Space 2 Address Map 52 8 2 6 Local Space 3 Address Map 52 8 3 IP Inter...

Page 6: ... USE NOTES 66 11 1 NVRAM Real Time Clock Control 66 12 TECHNICAL INFORMATION 67 12 1 Processor 67 12 2 Memory 67 12 3 Other Devices 67 12 4 VME Interface 67 12 5 Ethernet Interface 67 12 6 Asynchronous Serial Interface 68 12 7 PCI Expansion Connector 68 12 8 IndustryPack Interface 68 12 8 1 Logic Interface 68 12 8 2 I O Interface 68 12 9 Power Supply 68 12 9 1 Power Supply Scheme 68 12 9 2 Restric...

Page 7: ...T 27 FIGURE 4 3 I2C EEPROM CONTENT 29 FIGURE 5 1 BOOT FLASH COMMAND CYCLES 30 FIGURE 5 2 BOOT FLASH AUTO SELECT CODES 31 FIGURE 5 3 BOOT FLASH SECTOR MAP 31 FIGURE 5 4 MEMORY FLASH COMMAND CYCLES 33 FIGURE 5 5 MEMORY FLASH AUTO SELECT CODES 34 FIGURE 5 6 MEMORY FLASH SECTOR MAP 34 FIGURE 6 1 UNIVERSE II PCI HEADER 35 FIGURE 7 1 82551ER PCI HEADER 37 FIGURE 7 2 82551ER CONFIGURATION EEPROM SETTINGS...

Page 8: ...0 3 VME SYSTEM CONTROLLER JUMPER 56 FIGURE 10 4 STATUS INDICATORS 57 FIGURE 10 5 VME P1 CONNECTOR 59 FIGURE 10 6 VME P0 CONNECTOR 60 FIGURE 10 7 VME P2 CONNECTOR 61 FIGURE 10 8 IP P1 CONNECTOR 62 FIGURE 10 9 PCI EXPANSION CONNECTOR 64 FIGURE 10 10 SERIAL PORT A RS232 DB9 MALE CONNECTOR 64 FIGURE 10 11 SERIAL PORT B RS232 DB9 MALE CONNECTOR 65 FIGURE 10 12 ETHERNET CONNECTOR 8P RJ45 65 FIGURE 12 1 ...

Page 9: ...ore Timer DMA I2C Interrupt Controller Memory Controller PCI Arbiter FLASH Memory 1 Mbyte 8 bit wide socket Boot FLASH 8 Mbyte 64 bit wide on board Memory FLASH System Memory 64 Mbyte 64 bit wide synchronous DRAM 100 MHz VME Bus Interface Tundra Universe II VME PCI Bridge Ethernet Interface Intel 82551ER Fast Ethernet Controller IEEE 802 3 10Base T 100Base TX RJ45 Front I O IndustryPack Interface ...

Page 10: ... IndustryPack Bridge 4 IP Slots PCI to VME Bridge Tundra Universe II P 1 P 2 RJ45 PCI Local Bus 8 8 8 IP A IP B IP C IP D 10Base T 100Base TX P 0 64 64 32 Figure 1 2 Block diagram TVME8300 IP Slot A IP Slot C IP Slot D IP Slot B PCI Expansion P 2 P 1 TVME8300 xx P 0 P 2 P 1 P 0 VME64x Backplane TVME001TM 10 VME64 P0 P2 to 4x50 pin Flat Cable Connector SERIAL 1 SERIAL 2 FAIL FUSE LED ACT SYS LED LI...

Page 11: ...es two banks of FLASH memory Bank 0 consists of two 32 pin PLCC sockets each populated with a 512 K x 8 bit FLASH device for a total of 1 Mbyte 8 bit wide Boot FLASH memory Bank 1 consists of four 1 M x16 bit on board FLASH devices providing a total of 8 Mbyte 64 bit wide Memory FLASH memory 2 2 2 SDRAM Memory The TVME8300 provides 64 Mbyte 64 bit wide SDRAM memory build with four 8 M x 16 bit SDR...

Page 12: ...d status functions Please refer to the address map section of this manual for details 2 3 PCI Bus The TVME8300 implements a 32 bit 33 MHz PCI bus The following devices are available on the TVME8300 PCI bus MPC8245 Integrated Host PowerPC Processor Motorola Universe II VME PCI Bridge Tundra 82551ER Fast Ethernet Controller Intel PCI9030 PCI Target Chip PLX Technology Optional PCI Devices on PCI Exp...

Page 13: ...lease refer to the 82551ER manual for details 2 6 IndustryPack Interface The TVME8300 uses the PLX Technology PCI9030 PCI Target Chip to access the IndustryPack interface on the PCI bus Four single sized IP slots A D are provided Double sized IP modules 16 bit can be used on combined IP slots A B or IP slots C D The clock rate for each IP slot can be programmed to 8 MHz or 32 MHz The IP I O lines ...

Page 14: ...The following interrupt sources are available Utility Register ABORT Switch 82551ER Fast Ethernet Controller PCI9030 PCI Target Chip for IndustryPack Interface Universe II LINT0 VME PCI Bridge Universe II LINT1 VME PCI Bridge Universe II LINT2 VME PCI Bridge Universe II LINT3 VME PCI Bridge PCI Expansion INTA PCI Expansion Connector PCI Expansion INTB PCI Expansion Connector PCI Expansion INTC PCI...

Page 15: ...s System Controller Green Board Activity Green Board Failure Red Fuse Status Red LAN Link Status Green LAN Speed Status Green Please see the Board I O section for more details 2 11 Front Panel Switches The TVME8300 provides 2 momentary switches available at the TVME8300 front panel The following switches are available Reset Board Reset Abort CPU Interrupt Please see the Board I O section for more ...

Page 16: ...e 0 based 0xFE00_0000 0xFE00_FFFF 64K PCI I O Space 0 based 0xFE01_0000 0xFE7F_FFFF 8M 64K Reserved 0xFE80_0000 0xFEBF_FFFF 4M PCI I O Space 0 based 0xFEC0_0000 0xFEDF_FFFF 2M Configuration Address Register 0xFEE0_0000 0xFEEF_FFFF 1M Configuration Data Register 0xFEF0_0000 0xFEFF_FFFF 1M PCI Interrupt Acknowledge 0xFF00_0000 0xFF7F_FFFF 8M Memory FLASH 64 bit wide 0xFF80_0000 0xFFDF_FFFF 6M Reserv...

Page 17: ...0400_0000 0x3FFF_FFFF 1G 64M Reserved 0x4000_0000 0x7FFF_FFFF 1G Reserved 0x8000_0000 0xFCEF_FFFF 2G 49M PCI Memory Space 0xFCF0_0000 0xFCF0_0FFF 4K PCI accessible MPC8245 EUMB 0xFCF0_1000 0xFCFF_FFFF 1M 4K Reserved 0xFD00_0000 0xFDFF_FFFF 16M SDRAM Memory 0 Based 0xFE00_0000 0xFEFF_FFFF 16M Reserved 0xFF00_0000 0xFF7F_FFFF 8M Memory FLASH 64 bit wide 0xFF80_0000 0xFFDF_FFFF 6M Reserved 0xFFE0_000...

Page 18: ...al Devices Detail Address Start End Size Byte Description 0xFFE0_0000 0xFFE0_1FFF 8K NVRAM RTC 0xFFE0_2000 0xFFE3_FFFF 256K 8K Reserved 0xFFE4_0000 0xFFE4_0003 4 UTILITY REG 0xFFE4_0004 0xFFE7_FFFF 256K 4 Reserved 0xFFE8_0000 0xFFE8_0007 8 UART CH A 0xFFE8_0008 0xFFE8_000F 8 UART CH B 0xFFE8_0010 0xFFEF_FFFF 512K 16 Reserved Figure 3 6 Address Map Peripheral Devices Detail For read or write access...

Page 19: ...egister Detail 3 5 1 Control Register Bit Name Access Reset Function 0 MSB BOARD_RST R W 0 0 Normal Board Operation 1 Assert Board Reset 1 I2C_EEP_WE R W 0 0 I2C EEPROM Writes Disabled 1 I2C EEPROM Writes Enabled 2 MEM_FLASH_WE R W 0 0 Memory FLASH Writes Disabled 1 Memory FLASH Writes Enabled 3 BOOT_FLASH_WE R W 0 0 Boot FLASH Writes Disabled 1 Boot FLASH Writes Enabled 4 FUSE_INT_EN R W 0 0 Fuse...

Page 20: ...es OK 1 At least one Fuse triggered 5 SYSCON R 0 Not VME System Controller 1 VME System Controller 6 7 LSB Reserved Undefined for Reads Figure 3 9 Status Register Board initialization software should verify successful IP FPGA configuration All board fuses are recoverable fuses 3 5 3 Interrupt Register Bit Name Access Reset Function 0 MSB USR_INT R W 0 0 No User Interrupt Clear Interrupt 1 Active U...

Page 21: ...SB Reserved Write as 0 Undefined for Reads Figure 3 11 LED Register 3 5 5 Jumper Register Bit Name Access Reset Function 0 MSB JMP_0 R 0 Jumper 0 Open 1 Jumper 0 Closed 1 JMP_1 R 0 Jumper 1 Open 1 Jumper 1 Closed 2 JMP_2 R 0 Jumper 2 Open 1 Jumper 2 Closed 3 JMP_3 R 0 Jumper 3 Open 1 Jumper 3 Closed 4 5 6 7 LSB Reserved Undefined for Reads Figure 3 12 Jumper Register ...

Page 22: ...the Interrupt Register is set the Utility Interrupt is active User Interrupt To assert a user interrupt set the USR_INT bit in the Interrupt Register Write 0 to the USR_INT bit to clear the user interrupt Fuse Interrupt The FUSE_INT_EN bit in the Control Register controls whether an active fuse status is latched into the FUSE_INT bit in the Interrupt Register Write 1 to the FUSE_INT bit in the Int...

Page 23: ...on transfer size Data can be accessed multiple times at the CONFIG_DATA port until the CONFIG_ADDR port value is changed All of the MPC8245 Configuration Registers are intrinsically little endian Therefore all of the following Configuration Register settings are shown in little endian order Since on the TVME8300 the MPC8245 processor and peripheral logic operates in big endian mode software must e...

Page 24: ... Status Register Base Address Register 4 R W 0xFCF0_0000 0x18 Local Memory Base Address Register 1 4 R W reset_default 0x2C Subsystem Vendor ID 2 R W 0x0000 0x2E Subsystem ID 2 R W 0x0000 0x30 Expansion ROM Base Address 4 R 0x0000_0000 0x3C Interrupt Line 1 R W 0x00 0x3D Interrupt Pin 1 R 0x01 0x3E MIN GNT 1 R 0x00 0x3F MAX LAT 1 R 0x00 0x40 Bus Number 1 R W 0x00 0x41 Subordinate Bus Number 1 R W ...

Page 25: ...C Single Bit Error Counter Register 1 R W status 0xB9 ECC Single Bit Error Trigger Register 1 R W reset_default 0xC0 Error Enabling Register 1 1 R W reset_default 0xC1 Error Detection Register 1 1 R C status 0xC3 Processor Internal Bus Error Status Register 1 R C status 0xC4 Error Enabling Register 2 1 R W reset_default 0xC5 Error Detection Register 2 1 R C status 0xC7 PCI Bus Error Status Registe...

Page 26: ...mory Control Configuration Register 4 MCCR4 4 R W 0x2610_2220 Figure 4 1 MPC8245 Configuration Register Settings Board initialization software notes The MEMGO bit in the MCCR1 register offset 0xF0 must not be set until all other memory configuration parameters have been appropriately configured The DLL_RESET bit in the AMBOR register offset 0xE0 must be explicitly set and then cleared by software ...

Page 27: ...larity Interrupt Source 0 Level Low Utility Register 1 Edge Low ABORT Switch 2 Level Low 82551ER Ethernet 3 Level Low Reserved 4 Level Low PCI9030 IPAC 5 Level Low Universe II LINT0 VME 6 Level Low Universe II LINT1 VME 7 Level Low Universe II LINT2 VME 8 Level Low Universe II LINT3 VME 9 Level Low PCI Expansion INTA EXP 10 Level Low PCI Expansion INTB EXP 11 Level Low PCI Expansion INTC EXP 12 Le...

Page 28: ...4_1020 The mode bit in the GCR must be set for PIC mixed mode operation 4 2 3 2 Interrupt Configuration Register ICR Offset from EUMBBAR 0x4_1030 The ICR clock ratio field should be set to 0x2 for optimized interrupt performance The ICR SIE bit must be set to enable Serial Interrupt Mode 4 2 3 3 Serial Interrupt Vector Priority Registers SVPR The polarity and sense bits in the SVPRs must be config...

Page 29: ... for TVME8300 0x04 Board Option High Byte 0x05 Board Option Low Byte e g 0x000A for TVME8300 10 0x06 Board Version Major 0x07 Board Version Minor V major minor e g 0x0100 V1 0 0x08 0x0F Factory Reserved 0x10 0xFF Reserved Figure 4 3 I2C EEPROM Content The address of the on board I2C EEPROM is 0b000 Writes to the on board I2C EEPROM must be enabled in the Utility Control Register The check sum is t...

Page 30: ...the Utility Control Register The 8 bit wide socket Boot FLASH Socket XU1 must always be installed and provide the board initialization code at the system reset vector 0xFFF0_0100 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle Command Sequence Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 RA RD Reset 1 Base 0x000 0xF0 Base 0x000 MID Auto Select 4 Base 0x555 ...

Page 31: ... Read Address RD Read Data SA Sector Address WA Write Address WD Write Data Manufacturer Device Manufacture ID Device ID AMD 29F040B 0x01 0xA4 ST 29F040B 0x20 0xE2 Figure 5 2 Boot FLASH Auto Select Codes Sector Sector Size Byte Sector Address Range SA0 64K 0xFFF0_0000 0xFFF0_FFFF SA1 64K 0xFFF1_0000 0xFFF1_FFFF SA2 64K 0xFFF2_0000 0xFFF2_FFFF SA3 64K 0xFFF3_0000 0xFFF3_FFFF SA4 64K 0xFFF4_0000 0xF...

Page 32: ...ory FLASH address range is 0xFF00_0000 to 0xFF7F_FFFF For writes to the Memory FLASH double word 64 bit transfer sizes must be used Writes to the Memory FLASH must be enabled in the Utility Control Register For 64 bit writes to the Memory Flash the processor may issue a single beat 64 bit write using a caching inhibited stfd store floating point double with the data in a Floating Point Register FP...

Page 33: ... DID Write 4 Base 0x2_AAA8 0x00AA00AA 00AA00A Base 0x1_5550 0x00550055 00550055 Base 0x2_AAA8 0x00A000A0 00A000A0 WA WD Chip Erase 6 Base 0x2_AAA8 0x00AA00AA 00AA00A Base 0x1_5550 0x00550055 00550055 Base 0x2_AAA8 0x00800080 00800080 Base 0x2_AAA8 0x00AA00AA 00AA00A Base 0x1_5550 0x00550055 00550055 Base 0x2_AAA8 0x00100010 00100010 Sector Erase 6 Base 0x2_AAA8 0x00AA00AA 00AA00A Base 0x1_5550 0x0...

Page 34: ...cycle Symbols DID Device ID MID Manufacturer ID RA Read Address RD Read Data SA Sector Address WA Write Address WD Write Data Manufacturer Device Manufacturer ID Device ID SST 39VF160 0x00BF00BF00BF00BF 0x2782278227822782 SST 39VF1601 0x00BF00BF00BF00BF 0x234B234B234B234B SST 39VF1602 0x00BF00BF00BF00BF 0x234A234A234A234A Figure 5 5 Memory FLASH Auto Select Codes Sector Sector Size Byte Sector Add...

Page 35: ...he Line 0x0000_xx00 0x10 PCI Base Address 0 Configuration Register I O Mapped 0xFFFF_F001 1 4 Kbyte 0x14 PCI Base Address 1 Configuration Register Memory Mapped 0xFFFF_F000 1 4 Kbyte 0x18 PCI Unimplemented 0x0000_0000 0x1C PCI Unimplemented 0x0000_0000 0x20 PCI Unimplemented 0x0000_0000 0x24 PCI Unimplemented 0x0000_0000 0x28 PCI Reserved 0x0000_0000 0x2C PCI Reserved 0x0000_0000 0x30 PCI Unimplem...

Page 36: ...Reset will also trigger a TVME8300 board reset using the Universe II LRST output The Universe II VRSYSRST and VXSYSRST signals are mapped to the VME bus SYSRST signal Please see the Universe II user manual for details 6 4 Universe II Interrupts The Universe II LINT 4 7 interrupt pins are not used The Universe II LINT 0 3 interrupt pins are used as outputs and are mapped to the serial interrupts no...

Page 37: ...de Revision ID 0x0200_00xx 0x0C BIST Header Latency Cache Line 0x0000_xx00 0x10 PCI Base Address 0 Memory Mapped Configuration Register 0xFFFF_F000 1 4 Kbyte 0x14 PCI Base Address 0 I O Mapped Configuration Register 0xFFFF_FF81 1 64 Byte 0x18 PCI Base Address 0 Memory Mapped FLASH Space 0xFFFE_0000 1 128 Kbyte 0x1C Reserved 0x0000_0000 0x20 Reserved 0x0000_0000 0x24 Reserved 0x0000_0000 0x28 Reser...

Page 38: ...Ethernet Address Byte 2 0x01 xx 0x06 Ethernet Address Byte 5 Ethernet Address Byte 4 0x02 zz yy EEPROM ID 0x0A 0x4840 Subsystem ID 0x0B 0x1209 Subsystem Vendor ID 0x0C 0x8086 Reserved 0x0D Tbd Reserved 0x0E Tbd Reserved 0x0F Tbd Reserved 0x10 0x3E 0xFFFF EEPROM Checksum 0x3F variant Figure 7 2 82551ER Configuration EEPROM Settings 7 3 Media Capabilities IEEE 802 3 10Base T 100Base TX interface on ...

Page 39: ...arget Chip The PCI9030 provides four local spaces 0 3 that are used for accessing the TVME8300 IP interface The PCI9030 is accessible on the TVME8300 PCI bus device number 16 The PCI9030 INT interrupt output is mapped to serial channel no 4 of the MPC8245 PIC Basic PCI9030 register configuration is loaded from a serial EEPROM after power up or board reset Programming of the PCI9030 configuration r...

Page 40: ...ss 3 PCIBAR3 Local Space 1 IP A D I O ID INT Space 0xFFFF_FC00 1 1 Kbyte 0x20 PCI Base Address 4 PCIBAR4 Local Space 2 IP A D MEM Space 16bit 0xFE00_0000 1 32 Mbyte 0x24 PCI Base Address 5 PCIBAR5 Local Space 3 IP A D MEM Space 8bit 0xFF00_0000 1 16 Mbyte 0x28 Not Supported 0x0000_0000 0x2C Subsystem ID TVME8300 Subsystem Vendor ID TEWS TECHNOLOGIES 0x206C_1498 0x30 PCI Expansion ROM Base Address ...

Page 41: ... Space 1 Remap LAS1BA 0x0400_0001 0x1C Local Space 2 Remap LAS2BA 0x0000_0001 0x20 Local Space 3 Remap LAS3BA 0x0200_0001 0x24 Expansion ROM Remap EROMBA 0x0000_0000 0x28 Local Space 0 Descriptor LAS0BRD 0x1541_20A0 0x2C Local Space 1 Descriptor LAS1BRD 0x1541_20A2 0x30 Local Space 2 Descriptor LAS2BRD 0x1541_20A2 0x34 Local Space 3 Descriptor LAS3BRD 0x1501_20A2 0x38 Expansion ROM Descriptor EROM...

Page 42: ...ort Ext Reserved 0x0000 0x1E PCI 0x44 LSW Power Management Control Status PMCSR 14 8 0x0000 0x20 PCI 0x4A MSW Hot Swap Control Status Reserved 0x0000 0x22 PCI 0x48 LSW Hot Swap Next Capability Pointer Hot Swap Control HS_NEXT 7 0 HS_CNTL 7 0 0x0006 0x24 PCI 0x4E PCI Vital Product Data Address Reserved 0x0000 0x26 PCI 0x4C PCI Vital Product Data Next Capability Pointer PCI Vital Product Data Contro...

Page 43: ...al Exp ROM Descriptor EROMBRD 31 16 0x0000 0x62 Local 0x38 LSW Local Exp ROM Descriptor EROMBRD 15 0 0x0000 0x64 Local 0x3E MSW Local Chip Select 0 CS0BASE 31 16 0x0800 0x66 Local 0x3C LSW Local Chip Select 0 CS0BASE 15 0 0x0081 0x68 Local 0x42 MSW Local Chip Select 1 CS1BASE 31 16 0x0400 0x6A Local 0x40 LSW Local Chip Select 1 CS1BASE 15 0 0x0201 0x6C Local 0x46 MSW Local Chip Select 2 CS2BASE 31...

Page 44: ...FF 0xFFFF 0xFFFF 0xFFFF 0x90 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xA0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xB0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xC0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xD0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xE0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xF0 0xFFF...

Page 45: ...ce 2 32M 16 Big Mem IP A D MEM Space 16 bit port 3 16M 8 Big Mem IP A D MEM Space 8 bit port Figure 8 5 PCI9030 Local Space Assignment 8 2 2 Local Space 0 Address Map The PCI9030 local space 0 is used for the IP interface registers The PCI base address for local space 0 is PCIBAR2 at offset 0x18 in the PCI9030 PCI configuration register space Offset Base PCI Base Address 2 Size Byte Register 0x00 ...

Page 46: ...rface Register 8 2 3 1 Revision ID Register The Revision ID Register indicates the revision of the on board IP FPGA logic Bit Name Description 15 MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB REV_ID Read Only FPGA Logic Revision ID Figure 8 7 Revision ID Register ...

Page 47: ...ensitive 4 INT0_SENSE 0 IP Interrupt 0 Level Sensitive 1 IP Interrupt 0 Edge Sensitive 3 ERR_INT_EN 0 IP Error Interrupt Disabled 1 IP Error Interrupt Enabled 2 TIME_INT_EN 0 IP Timeout Interrupt Disabled 1 IP Timeout Interrupt Enabled 1 RECOVER 0 IP Recover Time Disabled 1 IP Recover Time Enabled 0 LSB CLKRATE 0 IP Clock Rate 8 MHz 1 IP Clock Rate 32 MHz Figure 8 8 IP Control Register After power...

Page 48: ...ET 0 LSB IP_A_RESET Read 0 IP RESET Signal on Slot x is De asserted 1 IP RESET Signal on Slot x is Asserted Write 1 to assert the IP RESET Signal on Slot x Automatic De assertion Write 0x000F to assert reset on all IP slots Figure 8 9 Reset Register The IP RESET signal is also asserted on all IP slots at power up or board reset Asserting IP reset by software does not reset the clock mode to 8 MHz ...

Page 49: ...to clear IP_A Timeout Status 11 ERR_D Read 0 No Error on IP_D 1 IP_D ERROR Signal Asserted Write No Effect 10 ERR_C Read 0 No Error on IP_C 1 IP_C ERROR Signal Asserted Write No Effect 9 ERR_B Read 0 No Error on IP_B 1 IP_B ERROR Signal Asserted Write No Effect 8 ERR_A Read 0 No Error on IP_A 1 IP_A ERROR Signal Asserted Write No Effect 7 INT1_D Read 0 No Interrupt 1 Request on IP_D 1 Active IP_D ...

Page 50: ...to clear Edge Sensitive IP_B Interrupt 0 Status 1 INT1_A Read 0 No Interrupt 1 Request on IP_A 1 Active IP_A Interrupt 1 Request Write 1 to clear Edge Sensitive IP_A Interrupt 1 Status 0 LSB INT0_A Read 0 No Interrupt 0 Request on IP_A 1 Active IP_A Interrupt 0 Request Write 1 to clear Edge Sensitive IP_A Interrupt 0 Status Figure 8 10 Status Register The IP timeout time is app 8µs An IP timeout o...

Page 51: ... INT Space 0x0000_0200 0x0000_027F 128 IP C I O Space 0x0000_0280 0x0000_02BF 64 IP C ID Space 0x0000_02C0 0x0000_02FF 64 IP C INT Space 0x0000_0300 0x0000_037F 128 IP D I O Space 0x0000_0380 0x0000_03BF 64 IP D ID Space 0x0000_03C0 0x0000_03FF 64 IP D INT Space Figure 8 11 Local Space 1 Address Map IP A D ID INT I O Space The TVME8300 will perform write cycles to the IP ID space Any access to the...

Page 52: ...e 8 12 Local Space 2 Address Map IP A D Memory Space 16 bit 8 2 6 Local Space 3 Address Map The PCI9030 local space 3 is used for the IP A D Memory space 8 bit port The PCI base address for local space 3 is PCIBAR5 at offset 0x24 in the PCI9030 PCI configuration register space Offset Base PCI Base Address 5 Start End Size Byte Description 0x0000_0000 0x003F_FFFF 4M IP A MEM Space 8 bit 0x0040_0000...

Page 53: ...No 4 read the IP Status Register PCI9030 Local Space 0 to determine the IP interrupt source Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register For using Error interrupts it is assumed that the IP module holds the asserted ERROR signal level and provides an acknowledge mechanism by register access to clear the error signal assertion If the IP module does n...

Page 54: ...Vendor ID 0x0000 0x0000 0x1498 Depends on PCI Exp Card Subsys ID 0x0000 0x0000 0x206C Depends on PCI Exp Card Vendor ID 0x1057 0x10E3 0x8086 0x10B5 Depends on PCI Exp Card Device ID 0x0006 0x0000 0x1209 0x9030 Depends on PCI Exp Card Device Number 13 14 16 Depends on PCI Exp Card PCI Device MPC8245 Integrated Host PPC Universe II VME PCI Bridge 82551ER Fast Ethernet Controller PCI9030 PCI target C...

Page 55: ...0 1 Board I O Overview IP Slot A IP Slot C IP Slot D IP Slot B PCI Expansion P 2 P 1 P 0 SERIAL 1 SERIAL 2 FAIL FUSE LED ACT SYS LED LINK 100M LED ABT Switch RST Switch 10 100BaseT J1 J2 PLD JTAG CPU JTAG BOOT 0 1 2 3 J5 1 2 3 SYS Figure 10 1 Board I O Overview ...

Page 56: ...served by the factory default boot initialization software The 8 bit wide socket Boot FLASH must always be installed and provide the board initialization code at the system reset vector If used the first instruction in the Memory FLASH must reside at address 0xFF00_0100 10 2 2 VME System Controller Jumper The VME system controller jumper is used to configure the VME system controller mode of the T...

Page 57: ...tivity LED Green is set by hardware control if there is any activity on the Local Memory bus or PCI bus 10 3 2 SYS LED The SYS System Controller LED Green is set by hardware control if the Universe II VME to PCI Bridge is the VME bus System Controller 10 3 3 FAIL LED The FAIL LED Red can be set by software control via the Utility LED Register to indicate a failure condition 10 3 4 FUSE LED The FUS...

Page 58: ...d reset is also performed at power up A board reset can also be asserted by software programming the Utility Control Register A board reset will perform a general board hardware reset re configuration of the IP FPGA PCI reset and CPU reset 10 4 2 ABT Switch The ABT ABORT switch can be used to generate a CPU interrupt The Abort Switch is mapped to serial interrupt no 1 of the MPC8245 PIC Serial int...

Page 59: ...2 GND VME_DS1 VME_BR0 VME_SYSRST VME_3 3V 13 VME_DS0 VME_BR1 VME_LWORD 14 GND VME_WRITE VME_BR2 VME_AM5 VME_3 3V 15 GND VME_BR3 VME_A23 16 GND VME_DTACK VME_AM0 VME_A22 VME_3 3V 17 GND VME_AM1 VME_A21 18 GND VME_AS VME_AM2 VME_A20 VME_3 3V 19 GND VME_AM3 VME_A19 20 GND VME_IACK GND VME_A18 VME_3 3V 21 VME_IACKIN VME_A17 22 GND VME_IACKOUT VME_A16 VME_3 3V 23 VME_AM4 GND VME_A15 24 GND VME_A7 VME_I...

Page 60: ...D_IO_38 IP_D_IO_39 IP_D_IO_40 GND 9 IP_D_IO_41 IP_D_IO_42 IP_D_IO_43 IP_D_IO_44 IP_D_IO_45 GND 10 IP_D_IO_46 IP_D_IO_47 IP_D_IO_48 IP_D_IO_49 IP_D_IO_50 GND 11 IP_C_IO_01 IP_C_IO_02 IP_C_IO_03 IP_C_IO_04 IP_C_IO_05 GND 12 IP_C_IO_06 IP_C_IO_07 IP_C_IO_08 IP_C_IO_09 IP_C_IO_10 GND 13 IP_C_IO_11 IP_C_IO_12 IP_C_IO_13 IP_C_IO_14 IP_C_IO_15 GND 14 IP_C_IO_16 IP_C_IO_17 IP_C_IO_18 IP_C_IO_19 IP_C_IO_20...

Page 61: ...GND IP_A_IO_17 VME_D16 IP_A_IO_18 IP_B_IO_16 15 IP_B_IO_17 IP_A_IO_19 VME_D17 IP_A_IO_20 IP_B_IO_18 16 GND IP_A_IO_21 VME_D18 IP_A_IO_22 IP_B_IO_19 17 IP_B_IO_20 IP_A_IO_23 VME_D19 IP_A_IO_24 IP_B_IO_21 18 GND IP_A_IO_25 VME_D20 IP_A_IO_26 IP_B_IO_22 19 IP_B_IO_23 IP_A_IO_27 VME_D21 IP_A_IO_28 IP_B_IO_24 20 GND IP_A_IO_29 VME_D22 IP_A_IO_30 IP_B_IO_25 21 IP_B_IO_26 IP_A_IO_31 VME_D23 IP_A_IO_32 IP...

Page 62: ...A2 40 ERROR 41 A3 42 INTREQ0 43 A4 44 INTREQ1 45 A5 46 STROBE 47 A6 48 ACK 49 RSV1 50 GND Figure 10 8 IP P1 Connector The following signals have an on board pull up resistor 4K7 3 3V RESET WRITE IDSEL IOSEL INTSEL MEMSEL ACK INTREQ0 INTREQ1 ERROR STROBE RSV0 RSV1 DMAREQ0 DMAREQ1 DMAACK DMAEND DMA is not supported on the TVME8300 IP interface 10 5 2 2 IP P2 Connector For each IP slot the IP P2 conn...

Page 63: ...R 22 SERR 23 LOCK 24 SDONE 25 DEVSEL 26 SBO 27 GND 28 GND 29 TRDY 30 IRDY 31 STOP 32 FRAME 33 GND 34 GND 35 ACK64 36 37 REQ64 GND 38 39 PAR 40 RST 41 C BE1 42 C BE0 43 C BE3 44 C BE2 45 AD1 46 AD0 47 AD3 48 AD2 49 AD5 50 AD4 51 AD7 52 AD6 53 AD9 54 AD8 55 AD11 56 AD10 57 AD13 58 AD12 59 AD15 60 AD14 61 AD17 62 AD16 63 AD19 64 AD18 65 AD21 66 AD20 67 AD23 68 AD22 69 AD25 70 AD24 71 AD27 72 AD26 73 ...

Page 64: ...nsion Connector type is AMP 2 767004 4 10 5 4 Serial Interface Connectors 10 5 4 1 Serial Port A Pin Signal Level 1 DCD input RS232 2 RXD input RS232 3 TXD output RS232 4 DTR output RS232 5 GND 6 DSR input RS232 7 RTS output RS232 8 CTS input RS232 9 RI input RS232 Figure 10 10 Serial Port A RS232 DB9 Male Connector 10 5 4 2 Serial Port B Pin Signal Level 1 DCD input RS232 2 RXD input RS232 3 TXD ...

Page 65: ...ort B RS232 DB9 Male Connector The serial port signals are shown in the TVME8300 pin function E g the TXD output line of the external device must be connected to pin 2 RXD input of the serial port connector not to pin 3 TXD output 10 5 5 Ethernet Interface Connector Pin Signal 1 TD 2 TD 3 RD 4 5 6 RD 7 8 Figure 10 12 Ethernet Connector 8P RJ45 ...

Page 66: ...48T59 NVRAM device The Real Time Clock function of the M48T59 device is turned off by default to save battery energy If the M48T59 Real Time Clock function has been turned off factory default it must be enabled again before using any other board resources e g Ethernet The PMON date command can be used to enable the Real Time Clock function Setup Start the Real Time Clock function PMON date 2004081...

Page 67: ... 100 MHz 8 Mbyte 64 bit wide Flash Memory 12 3 Other Devices 8 Kbyte NVRAM M48T59 with exchangeable battery 1 Mbyte 8 bit wide Boot Flash two PLCC sockets 12 4 VME Interface Tundra Universe II A16 A32 Master Slave Address Modes D08 D64 Master Slave Data Transfer Modes RR PRI VME bus Arbiter IRQ 1 7 any of seven IRQs System Controller Jumper Yes No Auto Detect Four Location Monitors DMA Controller ...

Page 68: ... two double size IP slots Spaces available for each IP slot 128 byte I O space 64 byte ID space 64 byte INT space 8 Mbyte MEM space 16 bit 4 Mbyte MEM space 8 bit Data bus width 16 bit Clock rate 8 MHz 32 MHz selectable for each IP slot 12 8 2 I O Interface VME64x IndustryPack I O on VME P0 P2 connectors 0 75A max continuous dc current per IP I O line 12 9 Power Supply 12 9 1 Power Supply Scheme T...

Page 69: ... max 2A total for IP slots C D IP slots C D fused for a total of 2A 12 9 3 2 12V Supply On board load Max 3mA Not needed for board system function only used in the 12V fuse status sensing logic Additional load optional I O PCI Expansion Connector Unfused additional limit by connector pin max current IP Interface Available on all IP slots max 1A per IP slot limited by number of 12V pins on IP conne...

Page 70: ...2 1 MTBF Data 12 10 2 Temperature Operating Temperature Range 0 C to 55 C forced air cooling Non Operating Temperature Range 40 C to 85 C 12 10 3 Weight TVME8300 10 365g 12 10 4 Humidity 5 to 90 Non Condensing 12 10 5 Form Factor One slot 6U VME 5 row z a b c d VME P1 P2 connectors VME64x P0 connector PCI expansion board occupies an additional VME slot if installed ...

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