TVME8300 User Manual Issue 1.4
Page 48 of 70
8.2.3.3 Reset
Register
The Reset Register can be used to assert the IP RESET# signal and to detect when the IP RESET#
signal is negated.
Bit
Name
Description
15
(MSB)
14
13
12
11
10
9
8
7
6
5
4
Reserved
Undefined for Reads
Write as ‘0’
3 IP_D_RESET
2 IP_C_RESET
1 IP_B_RESET
0
(LSB)
IP_A_RESET
Read :
0 : IP RESET# Signal on Slot x is De-asserted
1 : IP RESET# Signal on Slot x is Asserted
Write ‘1’ to assert the IP RESET# Signal on Slot x
(Automatic De-assertion).
Write 0x000F to assert reset on all IP slots.
Figure 8-9 : Reset Register
The IP RESET# signal is also asserted on all IP slots at power-up or board reset.
Asserting IP reset by software does not reset the clock mode to 8 MHz.
If 32 MHz clock mode is used, the clock mode should be reset to 8 MHz prior to asserting the IP
reset by software.
