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TPMC810 User Manual Issue 2.0.0
Page 10 of 22
4.3 Serial EEPROM Memory
The serial EEPROM memory contains by default the TEWS PCI Interface FPGA configuration data for
compatibility reasons. However, the entire configuration data are stored within and loaded from the
internal flash of the PCI target chip.
Address
Offset
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x00
0x032A
0x1498
0x0280
0x0000
0x0280
0x0000
s.b.
0x1498
0x10
0x0000
0x0040
0x0000
0x0100
0x4801
0x0001
0x0000
0x0000
0x20
0x0000
0x0006
0x0000
0x0003
0x0FFF
0xFE00
0x0000
0x0000
0x30
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0001
0x40
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x50
0x1502
0x4120
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x60
0x0000
0x0000
0x0000
0x0081
0x0000
0x0181
0x0000
0x0000
0x70
0x0000
0x0000
0x0030
0x0041
0x0078
0x0040
0x0224
0x96D0
0x80
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x90
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xA0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xB0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xC0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xD0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xE0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xF0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
Table 4-3 : Configuration EEPROM
Subsystem-ID Value (Offset 0x0C):
TPMC810-10 0x000A
TPMC810-20 0x0014