Tews Technologies TPCE260, User Manual

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TPCE260 User Manual Issue 1.0.3 Page 9 of 17
4 PCIe-to-PCI Bridge
PCI Configuration Registers
4.1.1 PCIe-to-PCI Bridge Configuration Space Header
PCI CFG
Register
Address
PCI Configuration Registers
Initial Values
(Hex Values)
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID E111 12D8
0x04 Status Command 0010 0000
0x08 Class Code Revision ID 060400 02
0x0C BIST Header Type Primary Latency
Timer
Cacheline Size 00 01 00 00
0x10 Reserved -
0x14 Reserved -
0x18 Secondary Latency
Timer
Subordinate Bus
Number
Secondary Bus
Number
Primary Bus
Number
00 00 00 00
0x1C Secondary Status I/O Limit I/O Base 02A0 01 01
0x20 Memory Limit Memory Base 0000 8000
0x24 Prefetchable Memory Limit Prefetchable Memory Base 0001 8001
0x28 Prefetchable Base Upper 32-Bit 00000000
0x2C Prefetchable Limit Upper 32-Bit 00000000
0x30 I/O Limit Upper 16-Bit I/O Base Upper 16-Bit 0000 0000
0x34 Reserved Capability Pointer 000000 80
0x38 Expansion ROM Base Address 00000000
0x3C Bridge Control Interrupt Pin Interrupt Line 00 00 01 00
Table 4-1 : PCIe-to-PCI Bridge Configuration Space Header