TMPE627 User Manual Issue 1.0.2
Page 15 of 34
The FPGA is connected to the status indicator of the PCI Express Mini Card Slot:
Signal
Bank
V
CCO
Pin
Description
LED_WWAN#
34
3.3 V
U1
WWAN status indicator
LED_WPAN#
34
3.3 V
V3
WPAN status indicator
LED_WLAN#
34
3.3 V
V2
WLAN status indicator
Table 4-10: FPGA General Purpose I/O
ADC Interface
4.7
The LTC2348 provide a pin-selectable SPI and LVDS serial interface. When the LVDS interface is active, the
inputs at the ADC are terminated with internal 100
Ω differential termination resistors.
Signal
Bank
V
CCO
Pin
Description
PD
15
3.3 V
B17
Power Down Input
LVDS/CMOS#
15
3.3 V
B16
I/O Mode Select
CNV
15
3.3 V
C12
Conversion Start
BUSY
15
3.3 V
D18
Busy Output
CS#
15
3.3 V
G16
Chip Select
SDI
15
3.3 V
G17
Data Input
SDO0
15
3.3 V
A17
Data Output 0
SDO1 / SDI+
15
3.3 V
D13
Data Output 1 / LVDS Data Input+
SDO2 / SDI-
15
3.3 V
C13
Data Output 2 / LVDS Data Input-
SDO3 / SCKI+
15
3.3 V
E13
Data Output 3 / LVDS Clock Input+
SCKI / SCKI-
15
3.3 V
D14
Clock Input / LVDS Clock Input-
SCKO / SCKO+
15
3.3 V
E15
Clock Output / LVDS Clock
SDO4 / SCKO-
15
3.3 V
D15
Data Output 4 / LVDS Clock
Output-
SDO5 / SDO+
15
3.3 V
E16
Data Output 5 / LVDS Data
SDO6 / SDO-
15
3.3 V
D16
Data Output 6 / LVDS Data Output-
SDO7
15
3.3 V
C18
Data Output 7
Table 4-11: ADC I/O Interface
Associated with the ADC are two additional signals. These are fault flags, provided by the ADC input
overvoltage protection. During normal operation the flags are high. During an overvoltage condition the flags
are pulled low.
Signal
Bank
V
CCO
Pin
Description
FF_12
15
3.3 V
B11
Fault flag for ADC channels 1 & 2
FF_34
15
3.3 V
E17
Fault flag for ADC channels 3 & 4
Table 4-12: ADC Fault Flag
