TMPE627 User Manual Issue 1.0.2
Page 13 of 34
Signal Name
Pin
Number
Direction
IO Standard
IO Bank
Drive
[mA]
Slew
Rate
OE<7>#
M15
OUTPUT
LVCMOS33
14
4
SLOW
OE<8>#
V11
OUTPUT
LVCMOS33
14
4
SLOW
OE<9>#
N14
OUTPUT
LVCMOS33
14
4
SLOW
OE<10>#
U16
OUTPUT
LVCMOS33
14
4
SLOW
OE<11>#
V17
OUTPUT
LVCMOS33
14
4
SLOW
OE<12>#
R15
OUTPUT
LVCMOS33
14
4
SLOW
OE<13>#
V16
OUTPUT
LVCMOS33
14
4
SLOW
SEL<0>
R2
OUTPUT
LVCMOS33
34
4
SLOW
SEL<1>
V8
OUTPUT
LVCMOS33
34
4
SLOW
Table 4-7: Digital I/O Interface
4.5.1 TTL I/O Interface
Each I/O line is buffered by a 74LVC2G241. The 74LVC2G241 is a tri-state buffer that provides TTL
compatible inputs with 5 V-tolerance. The outputs can be set to tri-state with an output enable signal and
provide a 47 Ω serial resistor and a 4.7 kΩ pull resistor. The pull resistor guarantees a valid logic level when
the outputs are tristate and not driven externally. The pull voltage can be set to 3.3 V, 5 V or GND. When set
to 5 V, the outputs must not be driven, but set to tristate for a valid high level.
A TVS array protects against ESD shocks.
DOx
OEx
47R
Protection
5V, 3.3V or GND
4k
7
F
P
G
A
IO_x
DIx
Figure 4-1: TTL I/O Interface
With the pull voltage set to 5 V, the digital I/O can weakly drive a higher voltage than 3.3 V by setting the
output to tri-state. This can be useful when connecting to a standard 5 V CMOS logic input, where a high
level of minimum 3.5 V is required. Drive DO constant low and use OE to toggle the output.
With the pull voltage set to GND, a pull-down functionality is implemented. Drive DO constant high and use
OE to toggle the output.
