Tews Technologies TIP606, User Manual

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TIP606 User Manual Issue 1.3 Page 11 of 15
4.5 Interrupt Enable Register Falling Edge
(INTENAHL)
Bit Symbol Description Access Reset
Value
15
.
.
.
0 Interrupt enable bit of corresponding channel for the falling
edge.
Bit 0 enables interrupts of input channel 1 and bit 15 enables
interrupt of input channel 15 for the falling edge.
1 = interrupt enabled
0 = interrupt disabled R/W
Figure 4-5 : Interrupt Enable Register Falling Edge (INTENAHL)
An interrupt on interrupt request line INTREQ0# of the IP bus is only generated if the global
interrupt enable bit of the Global Control Register is set to ‘1’. After power up or reset all bits of
this register are reset to ‘0’.
4.6 Interrupt Status Register Rising Edge
(INTSTATLH)
Bit Symbol Description Access Reset
Value
15
.
.
.
.
.
.
0 Interrupt status bit of corresponding input for the rising edge.
Bit 0 reflects the interrupt request state of input 1 and bit 15
reflects the interrupt request state of input 16 for the rising
edge.
Read ‘0’: no interrupt request pending
Read ‘1’: interrupt request pending
Write ‘1’: clear pending interrupt
After power up or reset all bits of this register are reset to ‘0’. R/W
Figure 4-6 : Interrupt Status Register Rising Edge (INTSTATLH)
4.7 Interrupt Status Register Falling Edge
(INTSTATHL)
Bit Symbol Description Access Reset
Value
15
.
.
.
.
.
.
0 Interrupt status bit of corresponding input for the falling edge.
Bit 0 reflects the interrupt request state of input 1 and bit 15
reflects the interrupt request state of input 16 for the falling
edge.
Read ‘0’: no interrupt request pending
Read ‘1’: interrupt request pending
Write ‘1’: clear pending interrupt
After power up or reset all bits of this register are reset to ‘0’. R/W
Figure 4-7 : Interrupt Status Register Falling Edge (INTSTATHL)