Test-Ok eC-test-mate Hardware Reference Manual Download Page 9

Copyright © TEST-OK. All Rights Reserved.

9 / 35

Digital Outputs (Group 101 and 102)

For optimal flexibility, the digital outputs are separated into two groups. The output voltage corresponding to
a '1' can be programmed separately for group 101. Group 102 has open drain outputs meaning that
'configuration' of the '1' output level must be done via an external pull-up resistor if necessary.
All outputs are switched off when communication is lost with the PC.

Group 101

Specifications:  V

outH

 = 2.5..24V,

V

outL

 = 0V

I

source

 max = 40mA, Isink Max 20mA,

R

out

 = 100Ω

Group 101, is protected against short circuit by means of a 100Ω series resistor. Clamping diodes protect
the outputs against voltages above 25V and below 0V if such voltages were inadvertently applied to the
outputs.

Note: the internal 100R resistor can only dissipate 100mW. E.g. when the output is programmed for 5V and
24V is applied on the corresponding EC-test-mate pin, then there will be a voltage of 18.5V across the 100R
resistor which would result in 3.4W dissipation!

Note: besides the maximum current, there is also a limit on dissipated power by the outputs. The total
power dissipated by bits 1..4 shall not exceed 500mW

Note: the configured output voltage of Group 101 is also used to determine the logic '1' output level of the
serial channel as long as the voltage is less or equal to 5V (above this voltage, the serial output is fixed to
5V independently of the Group 101 voltage)

Note: the outputs of group 101 are not rail-to-rail (LM324) and special care must be taken when the outputs
must sink a pull-up on the UUT. If the load to be sinked is less than 10kΩ, then an offset voltage will be
present on the output. As an example, if a 1KΩ pull-up to 5V is connected to an output, then the output
voltage will not go lower than 1.4V!!

Group 102

Group 102 consists of four 'open drain' outputs, pulling the output to GND via a 330R series resistor. The

Summary of Contents for eC-test-mate

Page 1: ...Copyright TEST OK All Rights Reserved 1 35 eC test mate Hardware Reference Manual Version 1 1 0 0 10 21 2014...

Page 2: ...Description 19 Analog Inputs 201 202 19 Digital Inputs 201 204 20 Digital Outputs Group 201 and 202 20 Bi Directional Digital I O 20 Serial Channel UART 201 20 RS485 RS485 201 21 CAN CAN 201 21 I2C I2...

Page 3: ...pter applying too high voltages may result in damage to the device Unlike the TEST OK fixture the Test Probes are connected directly to the Unit Under Test UUT hereafter without an intermediate nail b...

Page 4: ...er If the Unit Under Test UUT requires more test points then there are available on one or when the mix of required test functions is not available from a specific eC test mate type then it is possibl...

Page 5: ...ype I there are also references to the TEST OK Description Language TDL commands that can be used to control the functional blocks A block diagram of the eC test mate Type I is shown in the figure bel...

Page 6: ...pecifications Input impedance 1 8M Input range 100mV 24V Resolution 1 mV Accuracy 20mV or 0 2 Sampling rate 2kHz with digital filtering The maximum allowed input voltage that will not result in damage...

Page 7: ...rt circuit by means of a 100 series resistor Clamping diodes protect the outputs against voltages above 26V and below 0V if such voltages were inadvertently applied to the outputs All outputs are set...

Page 8: ...working input voltage is 24V Clamping diodes protect the inputs against voltages above 25V and below 0V The maximum allowed input voltage that will not result in damage is 31V Some of the inputs have...

Page 9: ...d for 5V and 24V is applied on the corresponding EC test mate pin then there will be a voltage of 18 5V across the 100R resistor which would result in 3 4W dissipation Note besides the maximum current...

Page 10: ...the input pins the open drain outputs have this series resistor as well resulting in a voltage divider This may cause unexpected behaviour is low resistance pull up resistors are present Associated te...

Page 11: ...st and guarantees that there is no unnecessary delay between the reception of data and the availability on the host The RxTimeout method allows to synchronize with the stream of bytes from the target...

Page 12: ...vantage is that the receiving software does not need to have any knowledge about the packet size If the packet contains bytes with the same value as STX and ETX then these values cannot be transmitted...

Page 13: ...rarily disconnect due to a reset of the USB circuitry Worst case voltage output accuracy is 0 25 When switched off the power supplies are disconnected from the connector Note that if a value lower tha...

Page 14: ...he pin is called BOARD_DETECT Note it is mandatory that the Board Detect pin of every eC test mate that is used in a test is connected to GND on the UUT when using the TEST TRACK or eC my test softwar...

Page 15: ...Digital Output 102 2 Input 0 24V Output Open drain 12 Digital Input 103 Digital Output 102 3 Input 0 24V Output Open drain 13 Digital Input 104 Digital Output 102 4 Input 0 24V Output Open drain 14 Di...

Page 16: ...Copyright TEST OK All Rights Reserved 16 35...

Page 17: ...Copyright TEST OK All Rights Reserved 17 35 Footprint technical drawings Type I...

Page 18: ...Copyright TEST OK All Rights Reserved 18 35...

Page 19: ...nds that can be used to control the functional blocks A block diagram of the eC test mate Type II is shown in the figure below As can be seen from the diagram the numbering of inputs outputs and other...

Page 20: ...outputs the line can be left floating by setting the output to 0 A pull up resistor shall be present on the UUT Serial Channel UART 201 The serial channel numbered as 201 is designed to work with sign...

Page 21: ...s RS485 driver will be in the high impedance state See section Serial Channel UART 101 for the configurable parameters baud rate etc Associated test command s CONFIG_RS485 TRANSMIT_RS485 RECEIVE_RS485...

Page 22: ...8V for longer periods to these test pins may damage the eC test mate Currently the SCL clock frequency is fixed at 100kHz Associated test command s I2C_START I2C_WRITE I2C_READ I2C_STOP Programmable...

Page 23: ...Digital Input 203 Digital Output 202 3 Input 0 24V Output Open drain 13 Digital Input 204 Digital Output 202 4 Input 0 24V Output Open drain 14 UART 201 VCC 0 5V typical 0 24V allowed 15 Digital Outpu...

Page 24: ...Copyright TEST OK All Rights Reserved 24 35...

Page 25: ...Copyright TEST OK All Rights Reserved 25 35 Footprint technical drawing Type II...

Page 26: ...Copyright TEST OK All Rights Reserved 26 35...

Page 27: ...s on the connectors of the eC test mate Type III there are also references to the TEST OK Description Language TDL commands that can be used to control the functional blocks A block diagram of the eC...

Page 28: ...e digital level goes from 0 to 1 at 1 5V while remains 1 until the voltage drops below 0 75V Digital Outputs Group 301 A total of seven digital outputs are provided The output voltage corresponding to...

Page 29: ...alog value in firmware 7 Analog Input 302 Digital Input 302 8 Analog Input 303 Digital Input 303 9 Analog Input 304 Digital Input 304 10 Analog Input 305 Digital Input 305 11 Analog Input 306 Digital...

Page 30: ...yright TEST OK All Rights Reserved 30 35 Max 7W or 1A when used with TEST Mate docking station Without the docking station the maximum depends on the power capabilities of the USB port 2W typical 22 G...

Page 31: ...Copyright TEST OK All Rights Reserved 31 35...

Page 32: ...Copyright TEST OK All Rights Reserved 32 35 Footprint technical drawing Type III...

Page 33: ...Copyright TEST OK All Rights Reserved 33 35...

Page 34: ...eC test mates to provide up to 7W instead of 2W when connected to a regular USB port Second eC test mates connected to the Docking Station are electrically isolated from the PC and from the mains pow...

Page 35: ...Copyright TEST OK All Rights Reserved 35 35 eC test mate Dimensions...

Reviews: