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R-Engine-D

Chapter 4: Software

4-19

By default, the SCC26C92 is enabled for both

transmit

and

receive

. This will allow for the use of an

485 operation is half-duplex only, which means

RS-232 in full-duplex mode. Once this is done, you can transmit and receive data as needed. If you do
need to do limited flow control, the MPO pin on the J1 header can be used for RTS. For a sample file
showing RS232 full duplex communications, please see r

e_scc.c

in the directory

tern\186\samples\re

.

RS485 is slightly more complex to use than RS232. RS
transmission does not occur concurrently with reception. The RS485 driver will echo back bytes sent to
the SCC. As a result, assuming you are using the RS485 driver installed on another TERN peripheral
board, you will need to disable

receive

while transmitting. While transmitting, you will also need to place

the RS485 driver in transmission mode as well. While you are receiving data, the RS485 driver will need
to be placed in receive mode.

s

n

_send_e/s

n

_rec_e

Arguments:

none

Return value:

none

This function enables transmission or reception on the SCC26C92 UART for channel

n

, where

n

can be

‘1’ or ’2’. After initialization, both of these functions are disabled by default. If you are using RS485,
only one of these two functions should be enabled at any one time.

Transmission and reception of data using the SCC is in most ways identical to SER0. The functions used

putser

n

er

n

etsers

n

h

nctions work for both SER1 and SER2, yet it is still important to remember that any function

cal

pass both COM arguments. Refer to the full definition of

s2_init()

for the format that

st be followed for all calls to SER2

low control is also handled in a mostly similar fashion. The follow table summarizes the flow control

sig

to transmit and receive data are similar. For details regarding these functions, please refer to the previous
section.

putsers

n

gets

g

T e above fu

l to SER2 must

mu

F

nals.

Channel

Flow control line SCC name Location on RE

SER1

RTS

OP0

J2 pin 27

SER1

CTS

IP0

J2 pin 36

SER2

RTS

OP1

J1 pin 3

SER2

CTS

IP1

J2 pin 24

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Summary of Contents for R-Engine-D

Page 1: ...thernet Interface Compact Flash interface with file system support ADC DAC based on the 40MHz Am186ER or 80MHz RDC R1100 Technical Manual 1724 Picasso Avenue Davis CA 95616 0547 USA Tel 530 758 0180 Fax 530 758 0181 Email sales tern com http www tern com ...

Page 2: ...0547 USA Tel 530 758 0180 Fax 530 758 0181 Email sales tern com http www tern com Important Notice TERN is developing complex high technology integration systems These systems are integrated with software and hardware that are not 100 defect free TERN products are not designed intended authorized or warranted to be suitable for use in life support applications devices or systems or in other critic...

Page 3: ... industrial process control and high speed data acquisition and especially ideal for OEM applications The RE has 32KB internal RAM which fulfills many embedded OEM products SRAM requirement No external SRAM would be required for an OEM version of the RE with Am186ER CPU only This increases system reliability while decreasing power consumption and cost The RE features fast execution times through 1...

Page 4: ... to be installed on the R Engine D A high speed up to 300K samples per second 8 channel 12 bit parallel ADC AD7852 can be installed This ADC includes sample and hold and precision internal reference and has an input range of 0 5 V The RE also supports a 4 channel high speed parallel DAC DA7625 0 2 5V 200KHz An optional 16 bit serial ADC ADS8344 100KHz successive approximation converter offering 8 ...

Page 5: ...directional I O lines from 82C55 PPI 512 byte serial EEPROM Supervisor chip 691 for reset and watchdog Real time clock DS1337 lithium coin battery optional 1 4 Physical Description The physical layout of the R Engine D is shown below J1 Header Address Data Expansion Bus 8 ch 16 bit ADC Dual 2 ch 12 bit DAC 4 ch 12 bit DAC 200KHz 8 ch 12 ADC 300KHz Step 2 Jumper J2 pins 38 40 SCC2692 Dual UART J2 H...

Page 6: ...oot loader resides in the top protected sector of the 256KW on board Flash chip 29F400 At power on or RESET the ACTF will check the STEP 2 jumper If STEP 2 jumper is not installed the ACTF menu will be sent out from serial port0 at 19200 baud If STEP 2 jumper is installed the jump address located in the on board serial EE see App E will be read out and the CPU will jump to that address A DEBUG ker...

Page 7: ...per set 3 See menu at hyper terminal 19 200 N 8 1 4 Type G08000 to jump to and execute code in SRAM 5 Set step 2 jumper cycle power Will execute code in SRAM at every power up 6 Test application 7 Return to Step 1 as necessary Step 1 Debug Mode 1 Launch Paradigm C C 2 Open rd ide in the tern 186 directory 3 Run samples 4 Use samples to build application in C C 5 Single step set breakpoints debug c...

Page 8: ...or a 256 KW SRAM the physical address is 0x00000 0x07ffff 3 The on board EE must have a Jump Address for the RE40_115 HEX with starting address of 0xfa000 4 The STEP2 jumper must be installed on J2 pins 38 40 For further information on programming the R Engine D refer to the Software chapter 1 6 Minimum Requirements for RD System Development 1 6 1 Minimum Hardware Requirements PC or PC compatible ...

Page 9: ...ct the debug serial port to your PC 2 2 1 Connecting the R Engine D to power and PC Install the power jack adapter into the T1 screw terminal You may use an ohm meter to confirm which pin is ground and which pin is 12V The diagram below also illustrates the correct orientation Plug the output of the wall transformer into the power jack adapter The RD will now power on With the step 2 jumper remove...

Page 10: ...Chapter 2 Installation R Engine D 2 2 Power Jack Adapter T1 Screw Terminal GND 12V Red Edge of debug cable aligned with Pin 1 of H2 Output of wall transformer ...

Page 11: ...nfiguration register and enhanced chip select functionality In addition the Am186ER has 32KB of internal volatile RAM This provides the user with access to high 3 3 RDC R1100 Introduction The RDC 1100 is based on RISC internal architecture It provides faster operation than the Am186ER 3 4 Am186ER Features Clock Due to its integrated clock generation circuitry the Am186ER microcontroller allows the...

Page 12: ...al UART INT2 J2 pin 19 also tied to alarm output of the DS1337 R INT3 J2 pin 21 used by the CS8900 Ethernet INT4 not tied to NMI J2 pin 7 noise immunity si These buffered external interrupt inputs require a falling edge HIGH to LOW to generate an interrupt used by the external Dual UART INT0 should not be used by application U9D INT1 J2 6 INT1 U2 55 U9C INT0 J2 8 INT0 U2 56 Remember that INT0 is u...

Page 13: ...as the clock input for the AD7852 Timer 0 should therefore not be used by application unless the AD7852 is not used The maximum rate at which each timer can operate is 10 MHz for the Am186ER and 20MHz for the R1100 since each timer is serviced once every fo cycles to respond to clock or gate events See the sample programs timer0 c and ae_cnt0 c in the samples ae directory PWM outputs The Timer0 an...

Page 14: ...ll up J2 pin 20 Input with pull up P1 Timer1 out Input with pull down J2 pin 29 or AD7852 Use as Clock f P2 PCS6 A2 Input with pull up J2 pin 27 Input with pull up P3 PCS5 A1 Input with pull up U4 pin 39 SCC2692 select P4 DT R Normal J2 pin 38 Input with pull up Step 2 P5 DEN DS Normal J2 pin 30 Input with pull up P6 SRDY Normal J2 pin 35 Input with external pull up P7 A17 Normal N A A17 P8 A18 No...

Page 15: ...c PDIR1 TxD0 RxD0 TxD PI outport 0xff76 0x2040 PIOM1 2 PCS6 RTC The itialize PIO pins void 2 2 will set P12 as output tput void pio char pio_wr 12 0 set P12 pin low if P12 is in output mode unsigned ing pin is in input mode io_rd 1 return 16 bit status of P16 P31 if corresponding pin is in input mode by the R Engine D system for on board components Error Reference source hat you are not interferi ...

Page 16: ... functions will transfer one byte or word of data to the specified I O address The external I O space is 64K ranging from 0x0000 to 0xffff The default I O access time is 15 wait states You may use the the I O wait states from 0 to 15 The system clock is 100 ns for both CPUs while the CPU clock is 25ns for the Am186ER and 12 5ns for the R1100 Details regarding this can be found in the Software chap...

Page 17: ...0 dat The call to inportb 0x020 will activate PCS0 as well as putting the address 0x20 over the address bus The decoder will select the 82C55 based on address lines A5 7 and the data bus will be used to read the appropriate data from the off board component Programmable Peripheral Interface 82C55A U5 PPI 82C55 is a low power CMOS programmable parallel interface unit for use in microcomputer system...

Page 18: ...e c t Figure 3 3 Mode Select Command Word The R Engine D maps U5 the 82C55 uPD71055 at base I O address 0x1A0 The ports registers are offsets of this I O base address The command register 0x1A6 Port 0 0x1A0 Port 1 0x1A2 Port 2 0x1A4 The following code example will set all ports to output mode outportb 0x1A6 0x80 mode 0 output all pins outportb 0x1A0 0x55 Port 0 alternating high low on pins outport...

Page 19: ...4 hour or 12 hour format with AM PM indicator The RTC is accessed via software drivers rtc_init and rtc_rds Refer to sample code in the samples re directory for re_rtc c The sample code is identical to the RDs predecessor the RE It is also possible to configure the real time clock to raise an output line attached to an external interrupt at 1 64 second 1 second 1 minute or 1 hour intervals This ca...

Page 20: ...which asserts RESET This automatic assertion of RESET may recover the application program if something is wrong After the R Engine D is reset the WDO remains low until a transition occurs at the WDI pin of the MAX691 When controllers are shipped from the factory the J9 jumper is off which disables the watchdog timer The Am186ER has an internal watchdog timer This is disabled by default with ae_ini...

Page 21: ...pling rate when in single channel mode as you do not have to wait for the on chip multiplexer to settle or delay associated with other control logic on the ADC The following table summarizes the signals to and from the ADC Please refer to the sample code in the 186 samples rd directory rd_ad16 c SCLK Serial clock from Am186ER OP3 Active low chip select Output from SC26C92 If low the ADC will have ...

Page 22: ...5 has an average settling time of 5 µs with a maximum settling time of 10µs Additional information is available in the tern_docs parts directory of the CD A sample program rd_da c may be found in the c tern 186 samples rd directory Compact Flash Interface By utilizing the compact flash interface on the RD users can easily add widely used 50 pin CF standard mass data storage cards to their embedded...

Page 23: ...igure 1 1 K 12V 12V GND SUB GND SUB Power Supply Solenoid O1 ULN2003 TinyDrive Figure 1 1 Drive inductive load with high voltage current drivers By default the high voltage drivers are configured to sinking drivers not sourcing and for output This requires the common substrate be tied to GND and the K voltage diodes are tied to the highest voltage in the system when driving inductive loads The U29...

Page 24: ...cluded in the rd ide project 3 8 Headers and Connectors The diagram below shows the location of pin 1 of each header on the RD Most signals on J1 and J2 header are routed directory to the CPU with no buffer protection This makes the CPU including SRAM Flash and other devices tied to the A D bus vulnerable to damage from out of range voltages The user is therefore responsible for ensuring that out ...

Page 25: ... 19 INT2 P25 18 17 P24 IP3 16 15 IP4 P11 14 13 P18 P10 12 11 P13 A19 10 9 P23 INT0 8 7 NMI INT1 6 5 SCLK P26 4 3 SDAT GND 2 1 OP0 J1 Signal VCC 1 2 GND OP1 3 4 CLK RxDB 5 6 GND TxDB 7 8 D0 VOFF 9 10 D1 BHE 11 12 D2 D15 13 14 D3 RST 15 16 D4 RST 17 18 D5 P16 19 20 D6 D14 21 22 D7 D13 23 24 GND HB 25 26 P12 D12 27 28 A7 WR 29 30 A6 RD 31 32 A5 D11 33 34 A4 D10 35 36 A3 D9 37 38 A2 D8 39 40 A1 Table ...

Page 26: ...ry mappings are done in software to define how translations are implemented by the hardware Implicit accesses to I O and memory address space occur throughout your program from TERN libraries as well as simple memory accesses to either code or global and stack data You can however explicitly access any address in I O or memory space and you will probably need to do so in order to access processor ...

Page 27: ...nto I O space since memory space is valuable and is reserved for uses related to the code and data Using I O mappings the address is output over the address bus and the returned 16 or 8 bit value is the return value For a further discussion of I O and memory mappings please refer to the Hardware chapter of this technical manual 4 1 Programming Overview The ACTF loader in the RD 512KB Flash will pe...

Page 28: ...8Install STEP2 jumper then power on 8Application program running in battery backed SRAM Battery lasts 3 5 years under normal conditions Start ParadigmC run RE_test ide Download code to target SRAM Edit compile link locate download and remote debug STEP 1 Debugging STEP 3 DV P Kit Generate application HEX file with DV P ACTF D to download L_29F40R HEX into SRAM Download application HEX file into FL...

Page 29: ... 0x20000 SRAM Flash For production the user must produce an ACTF downloadable HEX file for the application based on the DV Kit The application HEX file can be loaded into the on board Flash starting address at 0x80000 The on board EE must be modified with a G80000 command while in the ACTF PC HyperTerminal Environment The STEP2 jumper J2 pins 38 40 must be installed for every production version bo...

Page 30: ...s and interrupt settings you might wish to change With that in mind the basic effects of ae_init are described below For details regarding register use you will want to refer to the AMD Am186ER Microcontroller User s manual Initialize the upper chip select to support the default ROM The CPU registers are configured such that Address space for the ROM is from 0x80000 0xfffff to map MemCard I O wind...

Page 31: ...as the Real Time Clock might fail if the wait state is decreased too dramatically A function is provided for this purpose void io_wait Arguments char wait Return value none This function sets the current wait state depending on the argument wait wait 0 wait states 0 I O enable for 100 ns wait 1 wait states 1 I O enable for 100 25 ns wait 2 wait states 2 I O enable for 100 50 ns wait 3 wait states ...

Page 32: ...le Interrupt is special in that it can not be masked disabled The default ISR will return on interrupt void int0_init unsigned char i void interrupt far int0_isr void int1_init unsigned char i void interrupt far int1_isr void int2_init unsigned char i void interrupt far int2_isr void int3_init unsigned char i void interrupt far int3_isr void int4_init unsigned char i void interrupt far int4_isr vo...

Page 33: ...a reduced speed as well These timers are controlled and configured through a mode register that is specified using the software interfaces The mode register is described in detail in chapter 10 of the AMD AM186ER User s Manual The timers can be used to time execution of your user defined code by reading the timer values before and after execution of any piece of code For a sample file demonstratin...

Page 34: ...alid A sample program rd_ad12 c demonstrating the use of the AD7852 is included in tern 186 samples rd This sample code is already included in the rd ide project in the tern 186 directory Serial ADC ADS8344 The ADS8344 ADC unit U14 provides 11 channels of 0 5V analog inputs For details regarding the hardware configuration see the Hardware chapter To increase sampling speed on the 16 bit ADC the ne...

Page 35: ...he directory tern 186 samples rd void ra_da1 Arguments int dac Return value none This function drives the DAC at position U15 outputs are VA and VB The argument dac contains two pieces of information the value to be converted and the channel to output it on The argument dac must be constructed in the following format dac 0x2000 0x0FFF dac channel VA J4 16 dac 0x3000 0x0FFF dac channel VB J4 18 The...

Page 36: ...e real time clock can be accessed and programmed using two interface functions There is a common data structure used to access and use both interfaces typedef struct unsigned char sec1 One second digit unsigned char sec10 Ten second digit unsigned char min1 One minute digit unsigned char min10 Ten minute digit unsigned char hour1 One hour digit unsigned char hour10 Ten hour digit unsigned char day...

Page 37: ... 5 1998 Friday 13 55 30 the byte array would be initialized to unsigned char t 14 5 9 8 0 6 0 5 1 3 5 5 3 0 Delay In many applications it becomes useful to pause before executing any further code There are functions provided to make this process easy For applications that require precision timing you should use hardware timers provided on board for this purpose void delay0 Arguments unsigned int t...

Page 38: ...fault SER0 is used by the DEBUG kernel re40_115 hex for application download debugging in STEP 1 and STEP 2 The following examples that will be used show functions for SER0 but since it is used by the debugger you cannot directly debug SER0 This section will describe its operation and software drivers The following section will discuss SER1 and SER2 which pertain to the external SCC26C92 UART SER1...

Page 39: ...the nature of high speed baud rates and possible effects from the external environment serial input data will automatically fill in the buffer circularly without stopping regardless of overwrite If the user does not take out the data from the ring buffer with getser0 before the ring buffer is full new data will overwrite the old data without warning or control Thus it is important to provide a suf...

Page 40: ... COM structure should normally be manipulated only by TERN libraries It is provided to make debugging of the serial communication ports more practical Since it allows you to monitor the current value of the buffer and associated pointer values you can watch the transmission process typedef struct unsigned char ready TRUE when ready unsigned char baud unsigned char mode unsigned char iflag interrup...

Page 41: ...eturn value int return_value This function places one byte outch into the transmit buffer for the appropriate serial port The return value returns one in case of success and zero in any other case putsersn Arguments char str COM c Return value int return_value This function places a null terminated character string into the transmit buffer The return value returns one in case of success and zero i...

Page 42: ... To Send is not implemented are however functions available that allow you to check and set the value of these I O pins appropri w a please refer to the Am186ES User s Manual char sn_cts void Retrieves value of CTS pin void sn_rts char b Sets the value of RTS to b Completing Serial Communications our serial communications you can re initialize the serial port with s1_init to reset _close After com...

Page 43: ...function initializes SER1 with the specified parameters b is the baud rate value shown in Table 4 2 Arguments ibuf and isiz specify the input data buffer and obuf and osiz specify the location and size of the transmit ring buffer s2_init Arguments unsigned char b unsigned char ibuf int isiz unsigned char obuf int osiz COM ca COM cb Return value none This function initializes SER2 with the specifie...

Page 44: ... driver will need to be placed in receive mode sn_send_e sn_rec_e Arguments none Return value none This function enables transmission or reception on the SCC26C92 UART for channel n where n can be 1 or 2 After initialization both of these functions are disabled by default If you are using RS485 only one of these two functions should be enabled at any one time Transmission and reception of data usi...

Page 45: ...24 void s2_rts char b drives OP1 J1 3 Other SCC functions are similar hose for SER0 and SE sn_close clean_sern 4 6 Functio T p changed often Access to the EEPROM controller Part of the EEPROM is reserved for TERN use specifically for this purpose Addresses 0x00 to 0x1f on the EEPROM is reserved for system use including configuration information about the controller itself jump address for Step Two...

Page 46: ...ge drivers for the Compact Flash interface Refer to Chapter 4 of the lashCore technical manual tern_docs manuals flashcore pdf for a summary of the available routines he libraries and header files are as follows mm16 lib Libraries are found in the tern 186 lib directory and header files in the tern 186 include directory Refer to cf c and fs_cmds1 c im rd_cs89 c Ethernet controller rd_cf c Compact ...

Page 47: ...IP4 IP5 IP6 IP2 A1 A2 IP2 40 IP6 41 IP5 42 IP4 43 VCC 44 NC 1 A0 2 IP3 3 A1 4 IP1 5 A2 6 C E 3 9 R S T 3 8 X 2 3 7 X 1 3 6 R X D A 3 5 N C 3 4 T X D A 3 3 O P 0 3 2 O P 2 3 1 O P 4 3 0 O P 6 2 9 D0 28 D2 27 D4 26 D6 25 INT 24 NC 23 GND 22 D7 21 D5 20 D3 19 D1 18 A 3 7 I P 0 8 W R 9 R D 1 0 R X D B 1 1 N C 1 2 T X D B 1 3 O P 1 1 4 O P 3 1 5 O P 5 1 6 O P 7 1 7 U4 SCC2692 WR D0 D2 D4 D6 D7 D5 GND I...

Page 48: ...5 CS8900 TXDB XD XG GND VCC GND TXD TXD GND VCC VCC HC1 C25 10PF C26 10PF VCC RD2 GND GND D7 GND GND GND GND GND CF A4 VCC CF VCC WR2 VCC D15 INT4 RST VCC GND VCC D9 D8 D10 VCC A3 A1 D0 D2 A2 D1 GND GND VCC D0 D1 D2 D3 D4 D5 D6 D7 RST GND GND GND VCC VCC VCC TXDB RXDB TXDB GND OP1 GND RXDB TXDB RO 1 RE 2 DE 3 DI 4 VCC 8 B 7 A 6 GND 5 U02 LTC485 12VI D1 1N5817 1 2 3 4 5 U19 LM2575 12V 12V R15 1M C3...

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