78Q2120C09
MII Evaluation Board Design Kit
User Manual
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© 2007 Teridian Semiconductor Corporation, Proprietary and Confidential
- 7 -
Rev_1.2
PCB Layout Considerations
The following recommendations enhance the 78Q2120C09’s performance while minimizing EMC emissions:
1.
The transformer to transceiver signal traces must be 100 ohm differential transmission lines.
2.
Place the termination network components near the input data pins of the transceiver or transformer.
3.
Make all differential signal pairs short and of the same length.
4.
Decouple the transceiver thoroughly with 0.01µf and 0.1µf capacitors.
5.
Locate these decoupling capacitors as close as possible to the respective transceiver VCC and GND
pins.
6.
All decoupling capacitor and transceiver VCC and GND connections should tie immediately to a VCC or
GND plane via with minimum trace inductance.
7.
Total decoupling capacitance should be greater than the load capacitance that the digital output drivers
must drive.
8.
Use low inductance, ceramic surface mount decoupling capacitors.
9.
Use a multi-layer PCB with the inner layers dedicated to GND and VCC.
10.
A single VCC and GND plane is recommended for optimum performance. The lowest possible series
impedance is required between the analog and digital VCC and GND pins respectively of the transceiver.
11.
The outer layers of a 4 layer PCB are to be used for signal routing.
12.
Place the highest speed signals on the layer adjacent to the GND plane.
13.
Physically separate the analog signals from the digital signals by placing them on opposite layers or
routing them away from each other.
14.
Additional component and solder side ground layers may be added for maximum EMC containment.
15.
The GND plane should extend out to the transceiver side of the transformer. Remove the VCC and GND
planes from the line side of the transformer to the RJ-45 connector.
16.
Do not allow the chassis ground plane to cross over the transceiver GND plane. Minimum separation
must accommodate over 1.5KV.
17.
Provide onboard termination of the unused signal pairs in the CAT-5 cable.
18.
Use a shielded RJ-45 connector with its case stakes soldered to the chassis ground.
19.
Locate the transformer adjacent to the RJ-45 to minimize the shunt capacitance to the line.
20.
Minimize RF current fringing by making the VCC plane 0.10 inch smaller than the GND plane. If multiple
transceivers are used, provide partitions in the VCC and GND planes between the analog sections.
Maintain the partition from the transformer up to the transceiver’s analog interface. Do not cross these
partitions with signal traces, in particular any digital signals from adjacent transceivers.
21.
Add series resistors on all transceiver MII outputs to minimize digital output driver peak currents.
22.
Minimize the use of vias when routing the analog signal traces.
23.
Isolate the crystal and its capacitors from the analog signals with a guard ring.
24.
The crystal compensation capacitor value (C11 & C12) must be selected to trim the oscillator’s frequency
to 25.0000 MHz
±
50ppm. The optimum value will be layout dependent. A mere
±
4pf can shift the
25MHz
±
100Hz. The 25.0000 MHz
±
50ppm is specified by the IEEE.
Note: System vendors need to select the proper crystal according to their applications, such as operating
environment, product lifetime, and etc since crystal aging, operating temperature, and other factors can
affect the crystal frequency tolerance.
