Teridian 73S8009C User Manual Download Page 11

UM_8009C_059 

73S8009C Demo Board User Manual

 

 

Rev. 1.3 

 

11 

Item # 

(Figure 3) 

Electrical 
Schematic & 
PCB Silkprint 
Reference 

Name 

Use 

15 
18 

JP6 
JP5 

Card Polarity 
detect select 

The setting of these two jumpers depends on the 
type of smart card connector used (whether switch 
is nominally open or closed), and which of the card 
presence switch input of the 73S8009C is used.  In 
this demo board, the switch is nominally open.  The 
jumpers can be set in one of two ways: 

1.  Default setting: Use of PRES: JP5 must be 

set to PRES, and JP6 set to VDD 

2.  Alternative use: Use of 

PRES

: JP5 must be 

set to PREB, and JP6 set to GND 

Note: see board errata in the appendix for JP6 

16 

J5 

Smart Card 
Connector 

Smart card connector. 

When inserting a card (credit card size format), 
contacts must face up. 

17 

JP7 

CS Disable 

CS Disable Jumper.  Insertion of jumper disables 
the 73S8009CN.  The state of the 

CMDVCC#

CMDVCC%

 and RSTIN inputs will be latched and 

the I/OUC, AUX1UC and AUX2UC are tri-stated.  
The 

OFF

 and RDY outputs are also tri-stated.  

19 

TP9 

Vp Test Point 

Test point to monitor the internal intermediate 
voltage regulator.  This regulator output takes the 
VPC voltage and step it up to more than 5 V (if 
necessary) as the input source for the VCC and 
VDD output regulators. 

20 

J3 

Board VPC_IN 
supply, smart 
card data signals 
and 

OFF

 

Connector that supplies the VPC input supply 
voltage, the smart card data interface signals and 
the 

OFF

 interrupt output. 

 
 
 

Summary of Contents for 73S8009C

Page 1: ...Simplifying System IntegrationTM 73S8009C Demo Board User Manual February 10 2010 Rev 1 3 UM_8009C_059...

Page 2: ...the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves...

Page 3: ...t Points 9 4 Design Considerations 12 4 1 General Layout Rules 12 4 2 Optimization for Compliance with EMV 12 4 3 Power Supply Input Configurations 12 4 3 1 USB Power 12 4 3 2 Single Supply Power 12 4...

Page 4: ...ew 15 Figure 7 73S8009C Demo Board Top Signal Layer 16 Figure 8 73S8009C Demo Board Middle Layer 1 Ground Plane 16 Figure 9 73S8009C Demo Board Middle Layer 2 Supply Plane 17 Figure 10 73S8009C Demo B...

Page 5: ...e used in conjunction with the 73S12xxF evaluation platform 1 1 Package Contents Figure 1 73S8009C Demo Board The 73S8009C Demo Board Kit includes A 73S8009C Demo Board Rev 1 The following documents 7...

Page 6: ...oltage card interface 0 3 to VCC 0 3 VDC Pin Voltage LIN pin 0 3 to 6 5 VDC ESD Tolerance Card interface pins 6 kV ESD Tolerance Other pins 2 kV Pin Current 200 mA Operation outside these rating limit...

Page 7: ...ound pin Pin 9 Table 3 J4 Pin Descriptions Pin Pin Name Function 1 CMDVCC Controls the turn on output voltage value and turn off of VCC 2 CMDVCC 3 RSTIN Controls the card reset signal 4 RDY Indicates...

Page 8: ...8 to from the card 5 OFF Interrupt signal to the processor Indicator of card presence and any card fault conditions 6 GND Ground 7 GND Ground 8 GND Ground 9 VPC IN Must be between 2 7 V and 6 5 V 10 V...

Page 9: ...UM_8009C_059 73S8009C Demo Board User Manual Rev 1 3 9 3 Jumpers Switches and Test Points The items marked in Figure 3 are described in Table 5 Figure 3 73S8009C Demo Board Description...

Page 10: ...t VBUS Test point C4 CLK RST VCC I O C8 VBAT Input VBUS Input Two pin test points for each respective smart card signal The pin label name is the respective signal i e VCC CLK and the other pin is GND...

Page 11: ...ee board errata in the appendix for JP6 16 J5 Smart Card Connector Smart card connector When inserting a card credit card size format contacts must face up 17 JP7 CS Disable CS Disable Jumper Insertio...

Page 12: ...the smart connector to ground These capacitors serve as filters for CLK and RST signals in the case of long traces or test equipment perturbations The capacitor on CLK reduces ringing on the trace re...

Page 13: ...hed it can set the OFF_ACK signal high to shut off the 73S8009C If there is no need for the host to perform any shutdown tasks the OFF_ACK pin can be left open and it follows the state of the OFF_REQ...

Page 14: ...C3 OFF_REQ CS C4 4 7uF 1 2 3 JP6 1 2 3 JP5 1 2 TP5 1 2 3 JP3 1 2 TP7 1 2 TP8 1 2 TP4 1 2 TP6 1 2 JP4 3 3V Note JP4 pins 1 and 2 must not be connected with JP2 pins 1 and 2 at the same time GND C8 DNI...

Page 15: ...UM_8009C_059 73S8009C Demo Board User Manual Rev 1 3 15 5 2 73S8009C PCB Layouts Figure 5 73S8009C Demo Board Top View Figure 6 73S8009C Demo Board Bottom View...

Page 16: ...73S8009C Demo Board User Manual UM_8009C_059 16 Rev 1 3 Figure 7 73S8009C Demo Board Top Signal Layer Figure 8 73S8009C Demo Board Middle Layer 1 Ground Plane...

Page 17: ...UM_8009C_059 73S8009C Demo Board User Manual Rev 1 3 17 Figure 9 73S8009C Demo Board Middle Layer 2 Supply Plane Figure 10 73S8009C Demo Board Bottom Signal Layer...

Page 18: ...10_L_SV SSM_110_L_SV X SSM_110_L_SV Samtec 2 J2 J4 TSM_110_01_L_SV TSM_110_01_L_SV X TSM_110_01_L_SV Samtec 1 J5 Smart Card Connector ITT_CCM02 2504 401 1715 ND CCM02 2504LFT ITTCannon 1 J6 SIM SAM Co...

Page 19: ...ation The following 73S8009C documents are available from Teridian Semiconductor Corporation 73S8009C Data Sheet 73S8009C Demo Board User Manual 9 Contact Information For more information about Teridi...

Page 20: ...ected pin number for OFF_ACK in pin description 1 3 2 10 2010 Formatted in the new Teridian style Added Section 1 1 Package Contents Added Section 1 2 Safety and ESD Notes Added Table 3 J4 Pin Descrip...

Page 21: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Maxim Integrated 73S8009C DB...

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