Teridian 71M6534H, User Manual

Page: 62 / 87

71M6534H Demo Board User’s Manual
Page: 62 of 86
© 2005-2007 TERIDIAN Semiconductor Corporation
V2-0
Item #
Reference
Designator
Name Description
9 JP20 --
3-pin header for selecting the output driving the VARh
pulse LED. 1-2: RPULSE, 2-3: YPULSE.
A jumper is
normally installed from pin 1 to pin 2.
10 TP13 GND GND test point.
11 D6 VARS LED for VARh pulses
12
TP20
--
2-pin header enabling access to the selected pulse output
(DIO8, DIO6, OPT_TX) and V3P3.
TP21
2-pin header enabling access to the selected pulse output
(DIO7, DIO9) and V3P3.
13 JP19 SEG28/ DIO08
3-pin header for selecting the output driving the Wh pulse
LED. 1-2: WPULSE or OPT_TX, 2-3: XPULSE.
A jumper
is normally installed from pin 1 to pin 2.
14 D5 WATTS LED for Wh pulses
15 TP15 GND GND test point.
16 JP16 BAT MODE
3-pin header for selection of the firmware function in
battery mode. Plugging a jumper across pins 2 and 3 will
select 9600bd and will also disable the battery modes.
Plugging a jumper across pins 1 and 2 will select 300bd
and enable battery modes.
17 JP6 DIO3_R 3-pin header allowing access to the DIO03 pin.
18 TP16 GND GND test point.
19 JP7 ICE_EN
3-pin header for selection of the voltage for the ICE_E pin.
A jumper is normally installed between V3P3D and
ICE_E
, enabling programming of the 71M6534.
20
JP13, JP14,
JP15
DIO56, DIO57,
DIO58
2-pin headers providing access to the DIO pins DIO56,
DIO57, and DIO58.
21 U8 -- LCD with eight digits and 14 segments per digit.
22 J2 DEBUG 8X2 header providing access for the Debug Board.
23 -- -- The 71M6534 IC in LQFP-120 package.
24 TP8
CKTEST,
TMUXOUT
2-pin header providing access to the TMUXOUT and
CKTEST signals.
25 J18 SPI Interface
2X5 header providing access to the SPI interface of the
71M6534.
26 TP14 GND GND test point.
27 TP10 V1_R
3-pin header used to enable or disable the hardware
watchdog timer (WDT).
The WDT is disabled by plugging
as jumper between V1_R and V3P3 (default)
and
enabled by plugging as jumper between V1_R and GND.
28 J14 EMULATOR I/F
2x10 high-density connector port for connecting the
Signum ICE ADM-51 or the TFP-2 programmer.
29 J17 --
6-pin header providing access to the essential signals of
the emulator interface.
30
J19 IAN, IAP
2-pin headers providing access to the current input pins of
channel A, B, C and D, used in differential mode.
J20 IBN, IBP
J21 ICN, ICP
J22 IDN, IDP
31 TP17 VREF
1-pin header providing access to the VREF pin.