71M6534H Demo Board User’s Manual
Page: 53 of 86
© 2005-2007 TERIDIAN Semiconductor Corporation
V2-0
2.3 CALIBRATING AND COMPENSATING THE RTC
The real-time clock (RTC) of the 71M6534 is controlled by the crystal oscillator and thus only as accurate as the
oscillator. The 71M6534 has two rate adjustment mechanisms:
•
Analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0].
This adjustment is used to set the
oscillator frequency at room temperature close to the target (ideal) value. Adjusting
RTCA_ADJ[6:0]
will
change the time base used for energy measurements and thus slightly influence these energy
measurements. Therefore it is recommended to adjust the RTC before calibrating a meter.
•
Digital rate adjustment is used to dynamically correct the oscillator rate under MPU control. This is
necessary when the IC is at temperatures other than room temperature to correct for frequency
deviations.
The analog rate adjustment uses the I/O RAM register
RTCA_ADJ[6:0]
, which trims the crystal load capacitance.
Setting
RTCA_ADJ[6:0]
to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting
RTCA_ADJ[6:0]
to 3F maximizes the load capacitance, minimizing the oscillator frequency.
The maximum adjustment is approximately
±
60ppm. The precise amount of adjustment will depend on the
crystal and on the PCB properties. The adjustment may occur at any time, and the resulting clock frequency
can be measured over a one-second interval using a frequency counter connected to the TMUXOUT pin, while
0x10 or 0x11 is selected for the I/O RAM register
TMUX
[4:0]. Selecting 0x10 will generate a 1-second output;
selecting 0x11 will generate a 4-second output. The 4-second output is useful to adjust the oscillator at high
accuracy. It is also possible to set
TMUX
[4:0] to 0x1D to generate a 32.768kHz output.
The adjustment of the oscillator frequency using
RTCA_ADJ[6:0]
at room temperature will cause the 71M6534
IC to maintain the adjusted frequency
The digital rate adjustment can be used to adjust the clock rate up to
±
988ppm, with a resolution of 3.8ppm. The
clock rate is adjusted by writing the appropriate values to
PREG[16:0]
and
QREG[1:0]
. The default frequency is
32,768 RTCLK cycles per second. To shift the clock frequency by
Δ
ppm, calculate
PREG
and
QREG
using the
following equation:
⎟
⎠
⎞
⎜
⎝
⎛
+
⋅
Δ
+
⋅
=
+
⋅
−
5
.
0
10
1
8
32768
4
6
floor
QREG
PREG
PREG
and
QREG
form a single adjustment register with
QREG
providing the two LSBs. The default values of
PREG
and
QREG
, corresponding to zero adjustment, are 0x10000 and 0x0, respectively. Setting both
PREG
and
QREG
to zero is illegal and disturbs the function of the RTC.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC time as
necessary, using
PREG[16:0]
and
QREG[1:0]
.
The Demo Code adjusts the oscillator clock frequency using the parameters
Y_CAL
,
Y_CAL1
and
Y_CAL2
,
which can be obtained by characterizing the crystal over temperature. Provided the IC substrate temperature
tracks the crystal temperature, the Demo Code adjusts the oscillator within very narrow limits.
The MPU Demo Code supplied with the TERIDIAN Demo Kits has a direct interface for these coefficients and it
directly controls the
PREG[16:0]
and
QREG[1:0]
registers. The Demo Code uses the coefficients in the following
form:
1000
2
_
100
_
10
_
)
(
2
CALC
Y
T
CALC
Y
T
CAL
Y
ppm
CORRECTION
⋅
+
⋅
+
=
Note that the coefficients are scaled by 10, 100, and 1000 to provide more resolution.
Example: For a crystal, the deviations from nominal frequency are curve fitted to yield the coefficients a = 10.89,
b = 0.122, and c = –0.00714. The coefficients for the Demo Code then become (after rounding, since the Demo
Code accepts only integers):
Y_CAL
= -109,
Y_CALC
= 12,
Y_CALC2
= 7
