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MLT2 User Manual

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www.terasic.com

April 12, 2016

5.3 Demonstration for Terasic DE2-115 FPGA Board ................................................................................... 28

5.4 Demonstration Source Code ..................................................................................................................... 30

Chapter 6

Appendix ....................................................................................................................... 31

6.1 Revision History ....................................................................................................................................... 31

6.2 Copyright Statement ................................................................................................................................. 31

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Summary of Contents for MTL2

Page 1: ...p ...

Page 2: ... Layout 8 2 4 IDE Cable 11 2 5 ITG Adapter 11 Chapter 3 Using the MTL2 13 3 1 Pin Definition of 2x20 GPIO Connector 13 3 2 Using LCD 15 3 3 Using Terasic Multi touch IP 16 Chapter 4 ePhoto Demonstration 20 4 1 Operation Description 20 4 2 Block Diagram of the ePhoto Design 21 4 3 Loading Photos into FLASH 22 4 4 Demonstration for Terasic DE2 115 FPGA Board 23 4 5 Custom Display Photo 24 Chapter 5 ...

Page 3: ...T2 User Manual 2 www terasic com April 12 2016 5 3 Demonstration for Terasic DE2 115 FPGA Board 28 5 4 Demonstration Source Code 30 Chapter 6 Appendix 31 6 1 Revision History 31 6 2 Copyright Statement 31 ...

Page 4: ...ntains complete reference designs and source code for an ePhoto demonstration and Painter application This chapter provides the key information about the kit 1 1 1 1 A Ab bo ou ut t t th he e P Pa ac ck ka ag ge e The MTL2 kit comes with the following contents Multi touch LCD Module Second Edition IDE Cable with ITG Adapter 5V Power Supply Four Silicon Footstands Users can download MTL2 system CD ...

Page 5: ... l P Po ow we er r S Su up pp pl ly y f fo or r M MT TL L2 2 Figure 1 2 shows the power adapter for the MTL2 Due to the fact that the LCD panel in the MTL may consumes more power than some FPGA boards can provide a dedicated power adapter for MTL2 is required as shown in Figure 1 3 Figure 1 2 MTL2 Power Adapter ...

Page 6: ...April 12 2016 Figure 1 3 External USB Power Connection Setup 1 1 3 3 A As ss se em mb bl ly y Here are the procedures to assemble the MTL2 kit 1 Connect the IDE cable to the IDE connector on the back of the MTL as shown in the Figure 1 4 ...

Page 7: ... for the IDE cable 2 Place four silicon footstands to foot pegs of the MTL2 as shown in Figure 1 5 Figure 1 5 MTL2 Footstand Setup 1 1 4 4 C Co on nn ne ec ct ti iv vi it ty y The following figures show the connectivity for MTL2 to DE2 115 and DE1 SoC FPGA Development Boards ...

Page 8: ...re 1 6 MTL2 with DE2 115 Figure 1 7 MTL2 with DE1 SoC 1 1 5 5 G Ge et tt ti in ng g H He el lp p Here is information of how to get help if you encounter any problem Office Hours 9 00 a m to 6 00 p m GMT 8 Telephone 886 3 550 8800 Email support terasic com ...

Page 9: ...port Gesture support IDE interface 2x20 GPIO interface with ITG adapter 2 2 2 2 M MT TL L2 2 K Ki it t The MTL2 kit is assembled via three components Multi touch LCD Module IDE Cable IDE to GPIO ITG adapter The IDE cable is used to provide a high speed signal transmission for 33 MHz video signals The ITG adapter is designed to map the standard IDE pin assignment to the 2x20 GPIO interface on the F...

Page 10: ...l 9 www terasic com April 12 2016 Figure 2 1 MTL2 Top View The bottom view of MTL2 is shown in Figure 2 2 It depicts the layout and indicates the locations of connectors and key components Figure 2 2 MTL2 Bottom View ...

Page 11: ... MTL2 The IDE connector houses all the wires from peripheral interfaces connecting to the FPGA of a development kit through the IDE cable and ITG adapter Figure 2 3 Block Diagram of MTL2 Figure 2 4 illustrates the connection for MTL2 to the Terasic FPGA boards Figure 2 4 Connection Diagram of MTL2 Kit with Terasic FPGA boards ...

Page 12: ...d party IDE cables may cause the MTL2 to malfunction or even damage the module The IDE cable is shown in Figure 2 5 Figure 2 5 IDE cable 2 2 5 5 I IT TG G A Ad da ap pt te er r The IDE to GPIO ITG adapter is designed to remap IDE pins to GPIO pins Figure 2 6 and Figure 2 7 show the top view and bottom view of ITG adapter respectively The J1 connector is used to connect the FPGA board The J2 connec...

Page 13: ...MLT2 User Manual 12 www terasic com April 12 2016 Figure 2 6 ITG Adapter Top View Figure 2 7 ITG Adapter Bottom View ...

Page 14: ...ignals 3 3 1 1 P Pi in n D De ef fi in ni it ti io on n o of f 2 2x x2 20 0 G GP PI IO O C Co on nn ne ec ct to or r The 2x20 GPIO female connector is designed to directly connect to the 2x20 GPIO male connector on the Terasic FPGA development boards Figure 3 1 shows the signal names of the 2x20 GPIO from the ITG adapter Figure 3 1 2x20 GPIO Table 3 1 shows the recommended pin assignments for the ...

Page 15: ... Output 3 3 V LVTTL 14 MTL_G 0 Output 3 3 V LVTTL 15 MTL_G 1 Output 3 3 V LVTTL 16 MTL_G 2 Output 3 3 V LVTTL 17 MTL_G 3 Output 3 3 V LVTTL 18 MTL_G 4 Output 3 3 V LVTTL 19 20 21 MTL_G 5 Output 3 3 V LVTTL 22 MTL_G 6 Output 3 3 V LVTTL 23 MTL_B 0 Output 3 3 V LVTTL 24 MTL_G 7 Output 3 3 V LVTTL 25 MTL_B 1 Output 3 3 V LVTTL 26 MTL_B 2 Output 3 3 V LVTTL 27 MTL_B 3 Output 3 3 V LVTTL 28 MTL_B 4 Out...

Page 16: ... 2 and Figure 3 3 Table 3 2 LCD Horizontal Timing Specifications Item Symbol Typical Value Unit Min Typ Max Horizontal Display Area thd 800 DCLK DCLK Frequency fclk 26 4 33 3 46 8 MHz One Horizontal Line th 862 1056 1200 DCLK HS pulse width thpw 1 40 DCLK HS Blanking thb 46 46 46 DCLK HS Front Porch thfp 16 210 354 DCLK Table 3 3 LCD Vertical Timing Specifications Item Symbol Typical Value Unit Mi...

Page 17: ... M Mu ul lt ti i t to ou uc ch h I IP P Terasic Multi touch IP is provided for developers to retrieve user inputs including multi touch gestures and single touch The file name of this IP is i2c_touch_config v which is located in System CD IP folder The IP decodes I2C information and outputs coordinates and gesture information The inputs and outputs of this IP module is shown below ...

Page 18: ...signals in the 2x20 GPIO header respectively When touch activity occurs the control application should check whether the value of oREG_GESTURE matches a pre defined gesture ID defined in Table 3 4 and the relative X Y coordinates can be derived from oREG_X and oREG_Y Figure 3 1 shows the signaltap II waveform of the IP When the oREADY rises it indicates touch activity and the associated informatio...

Page 19: ...second touch point oREG_Y2 Output 9 bit Y coordinate of second touch point oREG_X3 Output 10 bit X coordinate of first touch point oREG_Y3 Output 9 bit Y coordinate of second touch point oREG_X4 Output 10 bit X coordinate of first touch point oREG_Y4 Output 9 bit Y coordinate of second touch point oREG_X5 Output 10 bit X coordinate of first touch point oREG_Y5 Output 9 bit Y coordinate of second t...

Page 20: ... Gestures and Its IDs Gesture ID hex Move Up 0x10 Move Left 0x14 Move Down 0x18 Move Right 0x1C Zoom In 0x48 Zoom Out 0x49 No Gesture 0x00 Note The Terasic IP Multi touch IP can also be found under the IP folder in the system CD as well as the reference designs ...

Page 21: ...demonstration implements a simple photo viewer Before running this demonstration three 800x480 photos should be vertically merged into one 800x1440 photo and be stored in FLASH of the FPGA board in advance In this demonstration users can browse each photo by using single touch move right or move left gesture to select the previous or next photo as shown in Figure 4 1 Figure 4 1 Select Next Photo b...

Page 22: ...retrieved photo data The VGA Controller retrieves the photo data at a rate of 60 photos per second Zoom handles the photo zooming process The displayed photo is zoomed before being sent to the LCD display When users touch the MTL2 screen I2C Touch Config will receive an interrupt signal from the touch screen When an interrupt is detected I2C Touch Config will read touch information from the touch ...

Page 23: ...le is connected to the host PC 2 Power on the FPGA Development Board 3 Execute the Control Panel application software Please refer to the user manual of the FPGA development kit for more information for the Control Panel software 4 Switch to the FLASH page and click on the Chip Erase xx Sec button to erase FLASH data 5 Click on the File Length checkbox to indicate that you want to load the entire ...

Page 24: ...d Figure 4 4 DE2 115 ePhoto Configuration Setup E Ex xe ec cu ut te e D De em mo on ns st tr ra at ti io on n Procedure to execute demonstration 1 Make sure the DE2 115 is powered off 2 Mount the ITG adapter onto the 2x20 GPIO 0 expansion header of the DE2 115 3 Connect the DE2 115 USB Blaster USB port to the PC USB Port with a USB Cable 4 Power on the DE2 115 FPGA Development Board 5 Make sure Qu...

Page 25: ... two fingers together to zoom the picture out Figure 4 5 Photo Display 4 4 5 5 C Cu us st to om m D Di is sp pl la ay y P Ph ho ot to o Procedure for creating custom photos for ePhoto 1 Prepare three 24 bit bitmap format photos with image resolutions of 800 width x 480 height pixels for each as shown in Figure 4 6 Figure 4 6 Original Photo Resolution ...

Page 26: ...r bitmap format The merged photo resolution should be 800 width x 1440 height pixels as shown in Figure 4 7 3 Use the tool bmp_to_raw exe in the Demonstrations RTL Photo directory to convert the picture to raw file This tool will removing bmp file header that help flash controller read the correct file data Figure 4 7 Photo Format for the ePhoto Demonstration ...

Page 27: ... The demonstration requires the following hardware Terasic FPGA Board Multi touch LCD Module 5 5 1 1 O Op pe er ra at ti io on n D De es sc cr ri ip pt ti io on n Figure 5 1 shows the Graphical User Interface GUI of the Painter Demo The GUI is classified into four separate areas Painting Area Gesture Indicator Clear Button and Color Palette Users can select a pen color from the color palette and s...

Page 28: ...tent from the associated video memory and VIP Video Out is used to display the display content The display content is drawn by the NIOS II processor according to user input For multi touch processing a Terasic Memory Mapped IP is used to retrieve the user input including multi touch gestures and single touch coordinates For IP usage details please refer to the Chapter Three in this document Note t...

Page 29: ...t ti io on n f fo or r T Te er ra as si ic c D DE E2 2 1 11 15 5 F FP PG GA A B Bo oa ar rd d This section shows how to setup the painter demo on the Terasic DE2 115 FPGA Board For other Terasic FPGA boards the setup procedures are similar H Ha ar rd dw wa ar re e S Se et tu up p Figure 5 4 Hardware Setup with DE2 115 ...

Page 30: ...MLT2 User Manual 29 www terasic com April 12 2016 Figure 5 5 Hardware Setup with DE1 SoC Figure 5 6 Hardware Setup with DE0 Nano Figure 5 7 Hardware Setup with DE0 CV ...

Page 31: ...L2_PAINTER demo_batch in the MTL System CD onto your system and execute test bat 7 Now you should see the painter GUI on the LCD 5 4 D De em mo on ns st tr ra at ti io on n S So ou ur rc ce e C Co od de e The source code locations of this demonstration for the various Terasic FPGA boards are shown in Table 5 1 Note The project is built under Quartus II 13 1 and both Altera VIP license and Terasic ...

Page 32: ...nary V1 0 1 Modify Figure 5 2 Description V1 0 2 Modify Figure 5 7 V1 0 3 Modify Figure 5 7 change DE0 nano soc to DE0 nano 6 6 2 2 C Co op py yr ri ig gh ht t S St ta at te em me en nt t Copyright 2016 Terasic Technologies All rights reserved We will continue to provide interesting examples and labs on our MTL2 webpage Please visit mtl2 terasic com for more information ...

Page 33: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0189 ...

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