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Decode Frame-valid, Line-valid and Data-valid to retrieve video raw data - Bayer Pattern
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Translate Bayer Pattern to RGB Data
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Streaming RGB based on Altera VIP and Streaming Specification
Figure 4-1
shows the system generic block diagram of demonstration reference design.
Figure 4-1 System Block Diagram of Aptina headboard Demonstration
14
4.2
4.2
Demonstration
for
Altera
DE2-115
FPGA
Board
Demonstration for Altera DE2-115 FPGA Board
This section shows how to setup the video demo on the Altera DE2-115 using camera resolution
800x600.
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Altera DE2-115 FPGA Board and USB Cable
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Terasic AHA-HSMC Daughter Card
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CMOS Image Sensor Headboard (MT9M023)
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VGA Display and VGA Cable
