Chapter 4
Demonstrations
This chapter shows how to control and retrieve video frames from an Aptina sensor headboard and
drive a display device to show the retrieved video. The demonstration requires the following
hardware:
•
FPGA Main Board with HSMC interface
•
Terasic AHA-HSMC daughter card
•
Aptina image sensor headboard
•
LCD Display
In the demonstration, Aptina MT9M023 headboard is used. If users use other Aptina image sensor
headboards, users will need to modify the design code by themselves for the demonstration to
work.
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4.1
4.1
Design
Concept
Design Concept
The reference design is developed based on Altera Video and Image Processing Suite (VIP). A
custom Camera VIP, provided by Terasic, is designed to retrieve raw image data from the image
sensor and decode the raw data to RGB data.
Before the FPGA can retrieve the raw data, the image sensor should be configured. In this
demonstration, the FPGA configure the registers in the image sensor through an I2C interface. The
configure items include: display area, PLL, and gain. Please note: the registers control is sensor type
dependent. Users need to refer the register data sheet provided by Aptina for register control.
The Camera VIP is a custom VIP-based on Altera VIP and Streaming specifications. It provides the
following processes:
