ADC-FMC User Manual
18
April 24, 2020
generator to the ADC_A_IN/ADC_B_IN/ADC_C_IN/ADC_D_IN port of the ADC-FMC
card through SMA cable (The output frequency should be more than 100KHz). The
ADC1_CLK and ADC2_CLK are come from two options below:
a)
TR5_CLK_OUT: Connect ADC1_CLK on ADC_FMC card to CLK_OUT_p (J1) on TR5
board, and connect ADC2_CLK on ADC-FMC card to CLK_OUT_n (J2) on TR5 board.
Set the SW1/SW2 on ADC-FMC card as ON.
b)
External 125MHz clock generator: Set the SW1/SW2 on ADC-FMC card as OFF if the
clock generator output signal is 3.3V standard, or set SW1/SW2 as ON if the output
signal is 2.5V.
3.
Make sure the FMC_A VADJ is set to 1.8V by shorting J5.7 and J5.8 as shown in
4.
Connect the USB Blaster II USB port J6 of the TR5 to the USB port of host PC with a Mini
USB cable.
5.
Power on the TR5 FPGA board.
6.
Make sure Quartus Prime and USB-Blaster II driver has been installed on the host PC.
7.
Copy the folder Demonstrations\TR5_ADC-FMCA\demo_batch from the ADC-FMC
System CD to the host PC and execute “test.bat” to configure the FPGA.
8.
Set SW[1:0] to 00 as shown in
9.
Double click “freq.stp” to launch Signal Tap Logic Analyzer.
10.
Click Start button on Signal Tap Windows, the ADC waveform will appear as shown in
. (It shows four channels Sine wave, because the four channels of the Analog
signal generator are all connected to the four ADC_In ports. If only one channel signal is
connected, only one sine wave will be shown in Signal Tap Logic Analyzer).
11.
Optionally, change SW[1:0] setting to select deference reference clock source for ADC
chips.
Figure 4-3 Short J5.7 and J5.8
Figure 4-4 SWITCH[1:0] on TR5
Summary of Contents for ADC-FMC
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