ADC-FMC User Manual
15
April 24, 2020
On-board SW1 and SW2 are designed to specify the voltage range of clock input to SMA connector.
When switches are off, the input clock voltage is expected to 3.3V. When switches are on, the input
clock voltage is expected to 2.5V.
If FPGA clock source is selected, developers need to provide difference clock source to
FPGA_CLK_ADC1_p/n and FPGA_CLK_ADC2_p/n.
Summary of Contents for ADC-FMC
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