Tenma 72-6851 & 72-6853 Instruction manual
Bit 7 -
FLT. This is the fault bit which will be set when an output fault is detected, i.e. an
execution error 002 has occurred.
Bit 6 -
RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains both the Requesting
Service message and the Master Status Summary message. RQS is returned in
response to a Serial Poll and MSS is returned in response to the
∗
STB? command.
Bit 5 -
ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4 -
MAV. The Message Available Bit. This will be set when the instrument has a
response message formatted and ready to send to the controller. The bit will be
cleared after the Response Message Terminator has been sent.
Bit 3 -
Not used.
Bit 2 -
Not used.
Bit 1 -
Not used.
Bit 0 -
LIM. The Limit status bit. This bit is set if any bits set in the Limit Event Status
Register correspond to bits set in the Limit Event Status Enable Register.
Status Model
18
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