SE868SY-D Hardware Design Guide
1VV0301705 Rev. 5
Page 17 of 44
2021-12-15
Not Subject to NDA
low power P/N, the DC-DC enable PIN (CE) must be connected to the SYS_ON signal,
exported on pin 5 of SE868SY-D, to ensure the module enters a deep sleep state.
Figure 4: Example of a Suitable 1.8 V DC-DC Converter
Figure 5: Example of a Suitable 0.8 V DC-DC Converter
Aluminum electrolytic capacitors are not recommended at the module input due to their
high ESR. When Tantalum capacitors are chosen, a minimum value of 10µF is
recommended, in parallel with a 0.1µF ceramic capacitor. Ceramic capacitors can be
used alone for both input and output, but ensure that the LDO is stable with such
capacitors tied to the output.
4.3.2.
Power Supply PCB Layout Guidelines
As seen on the electrical design guidelines, the power supply must have a low ESR
capacitor on the output to cut current peaks on the input and protect the module supply
from spikes.