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Telit Wireless Solutions NE866B1 Hardware Design Manual Download Page 35

NE866B1_Hardware_Design_Guide

1VV0301354 Rev. 6

Page

35

of

70

2018-02-28

A typical circuit for implementing an unconditional RESET is shown below:

NOTE:

In order to avoid a back powering effect it is recommended to avoid

having any HIGH logic level signal applied to the digital pins of the

NE866B1 when the module is powered off or during a reboot

transition.

Using bidirectional level translators which do not support High Z

mode during power off is not recommended.

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Summary of Contents for NE866B1

Page 1: ... 01 2017 Mod 0818 2017 01 Rev 0 NE866B1 HW Design Guide 1VV0301354 Rev 6 2018 02 28 ...

Page 2: ...s for copyrighted material including the exclusive right to copy reproduce in any form distribute and make derivative works of the copyrighted material Accordingly any copyrighted material of Telit and its licensors contained herein or in the Telit products described in this instruction manual may not be copied reproduced distributed merged or modified in any manner without the express written per...

Page 3: ...ivities IV Trademarks TELIT and the Stylized T Logo are registered in Trademark Office All other product or service names are the property of their respective owners V Third Party Rights The software may include Third Party Right software In this case you agree to comply with all terms and conditions imposed on you in respect of such separate software In addition to Third Party Terms the disclaime...

Page 4: ...NE866B1_Hardware_Design_Guide 1VV0301354 Rev 6 Page 4 of 70 2018 02 28 APPLICABILITY TABLE PRODUCTS NE866B1 E1 ...

Page 5: ...t 8 Text Conventions 9 Related Documents 10 2 GENERAL PRODUCT DESCRIPTION 11 Overview 11 Product Variants and Frequency Bands 11 Target market 12 Main features 12 TX Output Power 13 RX Sensitivity 13 Mechanical specifications 13 2 7 1 Dimensions 13 2 7 2 Weight 13 Temperature range 14 3 PINS ALLOCATION 15 Pin out 15 LGA Pads Layout 20 4 POWER SUPPLY 21 Power Supply Requirements 21 Power Consumptio...

Page 6: ...evels 31 Power On 32 Unconditional Restart 34 Power OFF procedure 37 Communication ports 38 5 5 1 Serial Ports 38 5 5 1 1 MODEM SERIAL PORT 1 38 5 5 1 2 MODEM SERIAL PORT 2 40 5 5 1 3 RS232 LEVEL TRANSLATION 40 General purpose I O 42 5 6 1 Using a GPIO as an INPUT 43 5 6 2 Using a GPIO as an OUTPUT 43 I2C Port 44 SIM Interface 44 5 8 1 SIMIN Detection 44 ADC Converter 44 6 RF SECTION 45 Bands Vari...

Page 7: ...otprint for the application 52 PCB pad design 53 PCB pad dimensions 54 Stencil 55 Solder paste 55 NE866B1 Solder reflow 56 9 PACKING SYSTEM 57 Tray 57 Tray Drawing 59 Tape Reel 60 Carrier Tape Drawing 61 Moisture sensitivity 61 10 CONFORMITY ASSESSMENT ISSUES 62 Declaration of Conformity 62 11 SAFETY RECOMMENDATIONS 63 READ CAREFULLY 63 12 REFERENCE TABLE OF RF BANDS CHARACTERISTICS 64 13 ACRONYMS...

Page 8: ...de and a starting point for properly developing your product with the Telit module Audience This document is intended for Telit customers especially system integrators about to implement their applications using the Telit module Contact Information Support For general contact technical support services technical questions and report documentation errors contact Telit Technical Support at TS EMEA t...

Page 9: ... failure or bodily injury may occur Caution or Warning Alerts the user to important points about integrating the module if these points are not followed the module and end user equipment may fail or malfunction Tip or Information Provides advice and suggestions that may be useful when integrating the module All dates are in ISO 8601 format i e YYYY MM DD ...

Page 10: ...e 1VV0301354 Rev 6 Page 10 of 70 2018 02 28 Related Documents SIM INTEGRATION DESIGN GUIDE 80000NT10001A NE866B1_NL865B1_AT_Commands_Reference_Guide 80534ST10817A Telit EVB User Guide 1VV0301249 xE866_IFBD_HW_USER_GUIDE 1VV0301368 ...

Page 11: ... NE866B1 the perfect platform to enable a quick implementation of LTE technology in IoT M2M where low cost and low power are more relevant than high speed The NE866B1 helps increase the addressable market for LTE technology to include a broad range of new applications and use cases best served with lower maximum data rate ultra low power reduced complexity and cost Some examples are smart metering...

Page 12: ...are required rather than high speed data for example Smart metering Smart parking Smart agriculture Waste collection Industrial sensors Healthcare monitors Home automation Main features Function Features Modem NB IoT cellular modem for low BW data communication Real Time Clock Internal IP stack Interfaces Main UART for AT commands Auxiliary UART I2C SPI GPIOs ADC Antenna ports ...

Page 13: ... Power class LTE All Bands Class 3 23dBm RX Sensitivity Product Band Sensitivity dBm NE866 B1 E1 B8 B20 113 Mechanical specifications 2 7 1 Dimensions The overall dimensions of NE866 family are Length 19 mm Width 15 mm Thickness 2 2 mm 2 7 2 Weight The nominal weight of the module is 1 5 grams ...

Page 14: ...perature Range 20 C 55 C The module is fully functional in all the temperature range and it fully meets the 3GPP specifications 40 C 85 C The module is fully functional in all the temperature range Storage and non operating Temperature Range 40 C 85 C Functional the module is able to make and receive data calls and SMS ...

Page 15: ...Comment Asynchronous Serial Port Prog Data SPI I2C GPIO A4 TXD I Serial data input from DTE CMOS 1 8V A5 RXD O Serial data output to DTE CMOS 1 8V B1 GPIO1 I O GPIO CMOS 1 8V Default function SPI_CS O SPI External CS CMOS 1 8V Alternate Function I2C_SDA I O I2C Data CMOS 1 8V Alternate Function A1 SPI_CLK O SPI Clock CMOS 1 8V ...

Page 16: ...Auxiliary UART TX Data to DTE CMOS 1 8V Primary Logging Port Default Function SPI_MOSI O SPI Master Data Out CMOS 1 8V Alternate Function GPIO2 I O GPIO CMOS 1 8V Alternate Function C2 GPIO3 I O GPIO CMOS 1 8V Default Function SPI_MISO I SPI Master Data In CMOS 1 8V Alternate Function I2C_SCL I O I2C Clock CMOS 1 8V Alternate Function ...

Page 17: ... Clock CMOS 1 8 A6 SIMIO I O External SIM Data I O CMOS 1 8 B5 SIMIN I SIM Presence input CMOS 1 8 See next chapters ADC F4 ADC_IN1 AI Analog Digital converter input A D RF Section G2 ANT I O LTE Main Antenna 50 ohm RF Miscellaneous Functions G4 RESET I Reset Input VBATT Pull up to VBATT 10Kohm G5 SLP_IND O Modem Sleep or PSM Indication CMOS 1 8 Do not Drive this pad G6 VAUX POWE RMON O 1 8V stabi...

Page 18: ... Baseband Power D1 GND Ground Power F1 GND Ground Power G1 GND Ground Power D2 GND Ground Power F2 GND Ground Power C3 GND Ground Power E3 GND Ground Power F3 GND Ground Power G3 GND Ground Power F6 GND Ground Power Reserved pins A2 RESERVED RESERVED A3 RESERVED RESERVED B2 RESERVED RESERVED B3 RESERVED RESERVED B4 RESERVED RESERVED B6 RESERVED RESERVED ...

Page 19: ... RESERVED C6 RESERVED RESERVED D4 RESERVED RESERVED D5 RESERVED RESERVED D6 RESERVED RESERVED D7 RESERVED RESERVED E4 RESERVED RESERVED E5 RESERVED RESERVED E6 RESERVED RESERVED E7 RESERVED RESERVED F5 RESERVED RESERVED F7 RESERVED RESERVED G7 RESERVED RESERVED WARNING Reserved pins must not be connected ...

Page 20: ...n please refer to the related SW documentation WARNING Reserved pins must not be connected A B C D E F G 1 SPI_CLK GPIO1 SPI_CS I2C_SDA TX AUX SPI_MOSI GPIO2 GND VBATT GND GND 2 RFU RFU GPIO3 SPI_MISO I2C_SCL GND VBATT GND ANT 3 RFU RFU GND LP_WAKE GND GND GND 4 TXD RFU RFU RFU RFU ADC_IN1 RESET 5 RXD SIM_IN RFU RFU RFU RFU SLP_IND 6 SIMIO RFU RFU RFU RFU GND VAUX PWRMON 7 SIMCLK SIMRST SIMVCC RFU...

Page 21: ...oltage 3 8V Nominal Supply Voltage Normal Operating Voltage Range 3 40 V 4 20 V Normal Operating Voltage Range Extended Operating Voltage Range 3 10 V 4 20 V Extended Operating Voltage Range NOTE The Operating Voltage Range MUST never be exceeded care must be taken when designing the application s power supply section to avoid having an excessive voltage drop If the voltage drop is exceeding the l...

Page 22: ...c T3412 10485 76s 175 min 246 3 µA C eDRX 10 24 sec AT PSM 1 4 µA Power Saving Enabled NB IoT Data Call 90mA BW 3 75KHz Single tone data call TX 0dBm 90mA BW 15KHz Single tone data call TX 0dBm 155 mA BW 3 75KHz Single tone data call TX 20dBm 155 mA BW 15KHz Single tone data call TX 20dBm 195 mA BW 3 75KHz Single tone data call TX 23dBm 195 mA BW 3 75KHz Single tone data call TX 23dBm Current cons...

Page 23: ... Battery 4 3 1 1 5V Source Power Supply Design Guidelines The desired output for the power supply is 3 8V hence there s not a big difference between the input source and the desired output and a linear regulator can be used A switching power supply will not be suited because of the low drop out requirements When using a linear regulator a proper heat sink shall be provided in order to dissipate th...

Page 24: ...peaks absorption In any case the frequency and Switching design selection is related to the application to be developed due to the fact the switching frequency could also generate EMC interferences For car PB battery the input voltage can rise up to 15 8V and this should be kept in mind when choosing components all components in the power supply must withstand this voltage A Bypass low ESR capacit...

Page 25: ...ption peaks a 100μF tantalum capacitor is usually suited Make sure the low ESR capacitor usually a tantalum one is rated at least 10V A protection diode should be inserted close to the power input in order to save the NB866B1 from power polarity inversion Otherwise the battery connector should be done in a way to avoid polarity inversions when connecting the battery The selected battery should be ...

Page 26: ...as always the time to cool down between the calls and the heat sink could be smaller than the calculated one for 300mA maximum RMS current or even could be the simple chip package no heat sink Moreover in the average network conditions the device is requested to transmit at a lower power level than the maximum and hence the current consumption will be less than the 195mA 23dBm being usually around...

Page 27: ... traces to the NB866B1 and the Bypass capacitor must be wide enough to ensure no significant voltage drops occur This is for the same reason as previous point Try to keep this trace as short as possible To reduce the EMI due to switching it is important to keep very small the mesh involved thus the input capacitor the output diode if not embodied in the IC and the regulator have to form a very sma...

Page 28: ...during module sleep mode PSM mode The operating range characteristics of the supply are Item Min Typical Max Output voltage 1 7V 1 80V 1 9V Output current 50mA Output bypass capacitor inside the module 100nF NOTE The Output Current MUST never be exceeded care must be taken when designing the application section to avoid having an excessive current consumption If the Current is exceeding the limits...

Page 29: ...with the network for a long time Additional hardware lines are defined to support this feature and to synchronize the activities with the external Host processor PIN DESCRIPTION Signal Function I O PAD LP_WAKE Low Power Wake Up Used to wakeup the NE866 from any of the low power modes either modem or apps I D3 SLP_IND Modem Sleep or PSM indication 0 NE866B1 modem is in Sleep mode PSM 1 NE866B1 mode...

Page 30: ...at either rising or falling edge or both edges In most cased the most convenient configuration is falling edge as shown in the application circuit below NOTE LP_WAKE is an analog input to a comperator but should be treated as a digital input from the application side Rising edge is considured when the signal crossed the level of 1 2V and going up Faling edge is considered when the signal crossed t...

Page 31: ...put low level 0V 0 35V Output high level 1 42V 1 85V Output low level 0V 0 2V LEAKAGE CURRENT CHARACTERISTICS Parameter AVG Input leakage current 10uA Output leakage current 10uA DRIVE STRENGTH Parameter AVG Max drive strength 10mA Parameter Min Max Input level on any digital pin CMOS 1 8 with respect to ground 0 3V 2 1V Input level on any digital pin CMOS 1 8 with respect to ground when VBATT is ...

Page 32: ...en VBATT is applied to the module VAUX PWRMON pin will be then set at the high logic level The following flow chart shows the proper turn on procedure PWRMON ON Modem ON Proc START PWR Supply ON PWRMON ON Delay 8 s AT Init Sequence Enter AT CR N Delay 1s 5s Y Y N Y Delay 8 sec N Start AT CMD AT Answer in 1sec Modem Reset Proc N Y ...

Page 33: ...1354 Rev 6 Page 33 of 70 2018 02 28 A flow chart showing the AT commands managing procedure is displayed below Start AT CMD START Delay 300 msec Enter AT CR Disconnect PWR Supply AT answer in 1 sec GO TO Modem ON Proc Start AT CMD END Y N ...

Page 34: ... pull up resistor may bring to latch up problems on the NE866B1 power regulator and improper functioning of the module The line RESET must be connected only in open collector configuration the transistor must be connected as close as possible to the RESET pin The unconditional hardware restart must always be implemented on the application board as the software must be able to use it as an emergenc...

Page 35: ...s shown below NOTE In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the NE866B1 when the module is powered off or during a reboot transition Using bidirectional level translators which do not support High Z mode during power off is not recommended ...

Page 36: ...wering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the NE866B1 when the module is powered OFF or during an ON OFF transition Using bidirectional level translators which do not support High Z mode during power off is not recommended Modem Reset Proc Reset LOW Delay 200ms Reset HIGH Delay 1s Apply Power On Procedure ...

Page 37: ... not used for a long time the below procedure should be followed in order to eliminate any possible damage due to unexpected power cut WARNING Please carefully follow the recommended procedure for shut down and power off Not following the recommended shut down and power off procedures might damage the device and consequently void the warranty Modem Power Off Proc AT CFUN 0 In PSM mode AT COPS 2 Ye...

Page 38: ...a level translator circuit may be needed to make the system work On the NB866B1 the ports are CMOS 1 8 5 5 1 1 MODEM SERIAL PORT 1 The serial port 1 on the NB866B1 is a 1 8V UART with only 2 RS232 signals It differs from the PC RS232 in the signal polarity RS232 is reversed and levels Serial port 1 is considered a low power UART and is avalable during LPM and PSM such that any activity in the TXD ...

Page 39: ...n side will be connected to the transmit line here named RXD For a minimum implementation only the TXD RXD lines can be connected In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the NB866B1 when the module is powered off or during a reboot transition Using bidirectional level translators which do not support High...

Page 40: ...ith SPI functionality SPI and AUX UART cannot work simultaniously 5 5 1 3 RS232 LEVEL TRANSLATION In order to interface the NB866B1 with a PC com port or a RS232 EIA TIA 232 application a level translator is required This level translator must invert the electrical signal in both directions Change the level from 0 1 8V to 15 15V The RS232 UART 16450 16550 16650 16750 chipsets accept signals with l...

Page 41: ...IM transceiver MAX218 In this case the chipset is capable to translate directly from 1 8V to the RS232 levels Example done on 4 signals only NOTE The digital input lines operating at 1 8V CMOS have an absolute maximum input voltage of 2 2V The level translator IC outputs on the module side i e module inputs will cause damage to the module inputs if the level translator is powered by a 3 8V supply ...

Page 42: ... AT Commands User Guide for more details on selecting the pads alternate functinality The following table shows the available GPIO s on the NB866B1 and their functionality PAD Signal Default Function Alt Func 1 I2C GPIO Alt Func 2 I2C Log Alt Func 3 GPIO Alt Func 4 SPI B1 GPIO1 GPIO1 I2C_SDA I2C_SDA GPIO1 SPI_CS C1 GPIO2 TX_AUX GPIO2 TX_AUX GPIO2 SPI_MOSI C2 GPIO3 GPIO3 I2C_CLK I2C_CLK GPIO3 SPI_M...

Page 43: ...en collector transistor with a 47K pull up to VAUX NOTE In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the NB866B1 when the module is powered off or during a powerup reboot transition Using bidirectional level translators which do not support High Z mode during power off is not recommended The VAUX PWRMON pin ca...

Page 44: ...ring PSM is an expected behavior For more info on SIM implementation please refer to the related User Guide SIM Holder Design Guides 80000NT10001a 5 8 1 SIMIN Detection PIN B5 is used as SIM DETECT input As long as SIMIN is not pulled low by the application board the module will use the internal eSIM For using an external SIM the user must assert SIMIN low NE866B1 modules ordered without eSIM supp...

Page 45: ...ance NB IoT 108 2dBm NOTE For low data rates sensitivity will be better than 3GPP spec RED requirements NE866B1 meets RED requirement Article 10 item 8 NE866B1 has been assessed to be used with separation distance more than 20cm NE866B1 reference antenna LTE MAGNETIC ANTENNA Type n T AT305 o 700 960MHz 1710 2700MHz o Antenna Gain 2 14dBi The maximum antenna gain for each frequency band is o FDD8 7...

Page 46: ...lines for a proper design The antenna and antenna transmission line on PCB for a Telit NB866B1 device shall fulfil the following requirements Item Value Frequency range Depending by frequency band s provided by the network operator the customer shall use the most suitable antenna for that those band s Bandwidth LTE Band VIII 900 80 MHz LTE Band XX 800 71 MHz 47 MHz Impedance 50 ohm Input power 23d...

Page 47: ... of the PCB used only for the Ground plane Surround on the sides over and under the antenna line on PCB with Ground avoid having other signal tracks facing directly the antenna line track The ground around the antenna line on PCB has to be strictly connected to the Ground Plane by placing vias every 2mm at least Place EM noisy devices as far as possible from NB866B1 antenna line Keep the antenna l...

Page 48: ... closed ring around it as shown below In that case the RF pin G2 should be routed through an internal layer of the board connecting to the PAD on the top layer ideally through a BLIND via VIA diameter should be chosen to achieve best coaxiality effect thorugh the board It is also recommended to bring directly to the reference RF ground layer the GND signal present on PADs F1 F2 F3 G1 and G3 6 5 3 ...

Page 49: ...e 49 of 70 2018 02 28 7 MECHANICAL DESIGN Mechanical Dimensions The NE866B1 overall dimensions are Length 19 mm Width 15 mm Thickness 2 2 mm Weight 1 5 gr 7 1 1 Mechanical Drawing 7 1 2 Top View The figure below shows mechanical top view of the NE866B1 ...

Page 50: ...NE866B1_Hardware_Design_Guide 1VV0301354 Rev 6 Page 50 of 70 2018 02 28 Dimensions are in mm 7 1 3 Bottom View as seen from bottom side ...

Page 51: ...NE866B1_Hardware_Design_Guide 1VV0301354 Rev 6 Page 51 of 70 2018 02 28 7 1 4 Side View ...

Page 52: ...sign_Guide 1VV0301354 Rev 6 Page 52 of 70 2018 02 28 8 APPLICATION PCB DESIGN The NB866B1 modules have been designed in order to be compliant with a standard lead free SMT process Recommended footprint for the application ...

Page 53: ...t is also suggested as common rule for an SMT component to avoid having a mechanical part of the application in direct contact with the module The area under WIRING INHIBIT see figure above must be clear from signal or ground paths PCB pad design Non solder mask defined NSMD type is recommended for the solder pads on the PCB PCB Copper Pad Solder Mask SMD Solder Mask Defined NSMD Non Solder Mask D...

Page 54: ...the PCB pads dimensions are described in the following image dimensions in mm It is not recommended to place via or micro via not covered by solder resist in an area of 0 3 mm around the pads unless it carries the same signal of the pad itself Holes in pad are allowed only for blind holes and not for through holes ...

Page 55: ...s issue should be discussed with the PCB supplier Generally the wettability of tin lead solder paste on the described surface plating is better compared to lead free solder paste It is not necessary to panel the application s PCB however in that case it is suggested to use milled contours and predrilled board breakouts scoring or v cut solutions are not recommended Stencil Minimum stencil thicknes...

Page 56: ...o TP 3 C second max Preheat Temperature Min Tsmin Temperature Max Tsmax Time min to max ts 150 C 200 C 60 180 seconds Tsmax to TL Ramp up rate 3 C second max Time maintained above Temperature TL Time tL 217 C 60 150 seconds Peak temperature Tp 245 0 5 C Time within 5 C of actual peak temperature tp 10 30 seconds Ramp down rate 6 C second max Time 25 C to peak temperature 8 minutes max ...

Page 57: ...us providing mechanical protection against transport stress In addition they are re usable and so environmentally sustainable There are 2 two antistatic rubber bands that enclose each envelope The carton box is rigid offering mechanical protection The carton box has one flap across the entire top surface It is sealed with tape along the edges of the box Table 1 Tray Packing Modules per Tray Trays ...

Page 58: ...NE866B1_Hardware_Design_Guide 1VV0301354 Rev 6 Page 58 of 70 2018 02 28 Tray organization is shown in the figure below ...

Page 59: ...NE866B1_Hardware_Design_Guide 1VV0301354 Rev 6 Page 59 of 70 2018 02 28 Tray Drawing WARNING These trays can withstand a maximum temperature of 125 ...

Page 60: ...Hardware_Design_Guide 1VV0301354 Rev 6 Page 60 of 70 2018 02 28 Tape Reel The NE866 modules are available on a T R packaging as well NE866B1 is packaged on reels of 200 pieces each as shown in the figure below ...

Page 61: ...e of the following conditions a Calculated shelf life in sealed bag 12 months at 40 C and 90 relative humidity RH b Environmental condition during the production 30 C 60 RH according to IPC JEDEC J STD 033A paragraph 5 c The maximum time between the opening of the sealed bag and the reflow process must be 168 hours if condition b IPC JEDEC J STD 033A paragraph 5 2 is respected d Baking is required...

Page 62: ...FORMITY ASSESSMENT ISSUES Declaration of Conformity Hereby Telit Communications S p A declares that the NB IOT Module is in compliance with Directive 2014 53 EU The full text of the EU declaration of conformity is available at the following internet address http www telit com red ...

Page 63: ...ng carefully the instruction for its use Do not insert or remove the SIM when the product is in power saving mode The system integrator is responsible for the functioning of the final product therefore care has to be taken to the external components of the module as well as any project or installation issue because the risk of disturbing the GSM network or external devices or having impact on the ...

Page 64: ...DMA 1900 B2 1850 1910 1930 1990 Tx 9262 9538 Rx 9662 9938 80 MHz WCDMA 1800 B3 1710 1785 1805 1880 Tx 937 1288 Rx 1162 1513 95 MHz WCDMA AWS B4 1710 1755 2110 2155 Tx 1312 1513 Rx 1537 1738 400 MHz WCDMA 850 B5 824 849 869 894 Tx 4132 4233 Rx 4357 4458 45 MHz WCDMA 900 B8 880 915 925 960 Tx 2712 2863 Rx 2937 3088 45 MHz WCDMA 1800 B9 1750 1784 8 1845 1879 8 Tx 8762 8912 Rx 9237 9387 95 MHz WCDMA 8...

Page 65: ... 900 B8 880 915 925 960 Tx 21450 21799 Rx 3450 3799 45 MHz LTE 1800 B9 1749 9 1784 9 1844 9 1879 9 Tx 21800 2149 Rx 3800 4149 95 MHz LTE AWS B10 1710 1770 2110 2170 Tx 22150 22749 Rx 4150 4749 400 MHz LTE 700a B12 699 716 729 746 Tx 23010 23179 Rx 5010 5179 30 MHz LTE 700c B13 777 787 746 756 Tx 27210 27659 Rx 9210 9659 31 MHz LTE 700b B17 704 716 734 746 Tx 23730 23849 Rx 5730 5849 30 MHz LTE 800...

Page 66: ... 748 758 803 Tx 27210 27659 Rx 9210 9659 45 MHz LTE TDD 2600 B38 2570 2620 2570 2620 Tx 37750 38250 Rx 37750 38250 0 MHz LTE TDD 1900 B39 1880 1920 1880 1920 Tx 38250 38650 Rx 38250 38650 0 MHz LTE TDD 2300 B40 2300 2400 2300 2400 Tx 38650 39650 Rx 38650 39650 0 MHz LTE TDD 2500 B41M 2555 2655 2555 2655 Tx 40265 41215 Rx 40265 41215 0 MHz ...

Page 67: ...Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access UART Universal Asynchronous Receiver Transmitter HSIC High Speed Inter Chip SIM Subscriber Identification Module SPI Serial Peripheral Interface ADC Analog Digital Converter DAC Digital Analog Converter I O Input Output GPIO General Purpose Input Output CMOS Complementary Metal Oxide Semiconductor MOSI Master Outp...

Page 68: ...1354 Rev 6 Page 68 of 70 2018 02 28 SRDY Slave Ready CS Chip Select RTC Real Time Clock PCB Printed Circuit Board ESR Equivalent Series Resistance VSWR Voltage Standing Wave Radio VNA Vector Network Analyzer RED Radio Equipment Directive ...

Page 69: ... 3 Updated Pinmap section Section 5 4 Added power down procedure Section 5 6 Updated GPIO alternate function description Section 5 7 Added I2C section 5 2017 11 16 Section 2 5 Remove Class 5 20dBm Section 3 1 Updated description of PSM pins Section 4 2 Added clarification related to measured values Section 4 5 Added more info related to PSM signals Section 5 5 Updated Serial port 1 description Sec...

Page 70: ... 01 2017 Mod 0818 2017 01 Rev 0 ...

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