GS2101M Low Power Wi-Fi Module Hardware User Guide
1VV0301395 Rev 3.0
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2017-11-13
2.1.3.
Network Services Subsystem
2.1.3.1.
APP CPU
The Network services subsystem consists of an APP CPU which is based on an ARM
CORTEX M3 core. It incorporates an AHB interface and a JTAG debug interface. The
network RTOS, network stack, and customer application code run on this CPU.
2.1.3.2.
Crypto Engine
The Network services subsystem contains a separate hardware crypto engine that
provides a flexible framework for accelerating the cryptographic functions for packet
processing protocols. The crypto engine has the raw generic interface for cipher and
hash/MAC functions such as AES, DES, SHA, and RC4. It also includes two optional
engines to provide further offload; the PKA and RNG modules. These provide additional
methods for public key acceleration functions and random number generation. The
engine includes a DMA engine that allows the engine to perform cryptographic operation
on data packets in the system memory without any CPU intervention.
2.1.4.
Memory Subsystem
The GS2101M module contains several memory blocks.
2.1.4.1.
SRAM
The system memory is built with single port and dual port memories. Most of the memory
consists of single port memory. A 64KB dual port memory is used for exchange of data
between the two CPU domains. All the memories are connected to the system bus
matrix in each CPU subsystem. All masters can access any of the memory within the
subsystem.
The APP subsystem has 384KB of dedicated SRAM for program and data use. The
WLAN subsystem has 320KB of dedicated SRAM for program and data use.
These memories are divided into banks of 64KB each. The bank structure allows
different masters to access different banks simultaneously through the bus matrix
without incurring any stall. Code from the external Flash is loaded into the SRAM for
execution by each CPU.
In addition, a static shared SRAM is provided. This consists of five 64KB memory blocks.
At any time, any of these memory blocks can be assigned to one of the CPU subsystem.
These should be set up by the APP CPU SW at initialization time. The assignment is not
intended to change during operation and there is no HW interlock to avoid switching in the
middle of a memory transaction. The assignment to the WLAN CPU should be done
starting from the highest block number going down to lowest block number. This result in
the shared memory appearing as a single bank for each CPU subsystem, independent of
the number of blocks assigned. The shared memory is mapped such that the SRAM
space is continuous from the dedicated SRAM to shared SRAM.
2.1.4.2.
ROM
ROM is provided in each CPU subsystem to provide the boot code and other functional
code that are not expected to change regularly. Each CPU has 512KB of ROM
2.1.4.3.
OTP ROM
The GS2000 device includes a 64Kbit OTP ROM used for storing MAC ID and
calibration information. The APP and WLAN subsystem each contain 32Kbits (4Kbytes)
of OTP memory.
