GS2011M Low Power Wi-Fi Module Hardware User Guide
1VV0301482 Rev. 5.0 Page
33
of
69
2018-01-10
2.2.6.4 I2C Interface
The I
2
C interface block implements the standard based two wire serial I2C protocol. The
interface can support both master and slave modes. It supports multiple masters, high speed
transfer (up to 3.4MHz), 7 or 10-bit slave addressing scheme, random and current address
transfer. It also supports clock stretching to interface with slower devices. It can generate
interrupts to the CPU to indicate specific events such as FIFO full/empty, block complete,
no ack error, and arbitration failure.
2.2.6.5 GPIO
The GPIO block provides programmable inputs and outputs that can be controlled from the
CPU SW through an APB interface. Any number of inputs can be configured as an interrupt
source. The interrupts can be generated based on the level or the transition of a pin. At reset,
all GPIO lines defaults to inputs. Each pin can be configured as input or output from SW
control.
2.2.6.6 ADC
The ADC is a 12-bit, low-power, A-to-D converter capable of running at up to 2 Mbps.
The ADC is accessible from the APP CPU only. The ADC contains an internal band-gap
reference which provides a stable 1.4V reference voltage. Alternatively, the ADC can be
programmed to use the VIN_3V3 external supply reference as the full-scale reference.
The ADC uses an input clock range of 10KHz to 2MHz. The input clock is generated by
an internal NCO (Number Controlled Oscillator). A conversion requires 1 clock cycles.
The ADC supports three measurement modes, continuous, single or periodic.
The sample data will be stored in a CPU readable FIFO. The file is an 8-deep FIFO. The
FIFO has SW configurable level interrupt. New samples are dropped if FIFO is full and
new data is received prior to FW servicing the FIFO, then the sample is dropped.
2.2.6.7 PWM
The PWM consists of three identical PWM function blocks. The PWM function blocks can
be used in two modes of operations:
•
Independent PWM function blocks providing output signal with programmable
frequency and duty cycle
•
Synchronized PWM function blocks with programmable phase delay between
each PWM output
The PWM has the following features:
•
32-bit AMBA APB interface to access control, and status information
•
Three identical PWM function blocks
•
Each PWM block can be enabled independently
•
All three PWM blocks can be started synchronously or chained with
programmable delay
Summary of Contents for GainSpan GS2011M
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