S42M Hardware User Guide
1VV0301379 Rev. 4
Page
14
of
48
2018-11-28
Reset
S42M are equipped with circuitry for generating reset from two sources:
•
A reset is held active, when VSUP falls below the threshold of the Supply Voltage
Monitor (V
IT- =
1,67V), and is released when VSUP rises above V
IT-
+ V
HYST
.
•
By holding pin B-1 (EXT-
RES#) at ≤ VSUP*0,3V for t
HOLDRESETNORMAL
≥ 0,2µs, an
external reset (
pin reset
) is generated. This pin has a fixed internal pull-up resistor
(R
PU
= 10k
Ω ... 30kΩ). EXT-RES# may be left open if not used.
S42M
E-6,F-6
VSUP
GND
+3V3
EXT-RES#
B-1
Reset-Switch is optional
Please Note: EXT-RES# of S42M has a 20k (range 10k to 30k) internal pullup.
Reset signal is optional
Host MCU
GPIO
VDD
Figure 4: S42M Example Reset
The following table shows the pin states of S42M during reset active.
Pin Name
State: S42M
EXT-RES#
Input with pull-up
typ. 20kΩ
XL-IN
Input
XL-OUT
Output
SWDIO
Input with pull-up
(1)
SWCLK
Input with pull-up
(1)
all other port pins
Input with pull-down
(1)
(1)
pull-up, pull-down: R
PU,
R
PD
is typ. 10k
Ω
Table 1: Pin States during Reset
If a logic signal driving EXT-RES# does not go fully to VSUP, some additional current is
drawn as a result of the internal pullup resistor on EXT-RES#. To minimize current draw,
an open drain driver or a logic-level FET as shown in Figure 5 can be used.
S42M
20k
EXT-RES#
VSUP
RES
EXT-RES
Figure 5: EXT-RES# with external FET
Summary of Contents for BlueMod+S42M
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