
10
10-2. Digital output terminal
EIA RS-644 (LVDS)
Driver output voltage:
±
350mV [Differential output] / 100
Ω
Total clock counts
1848CLK / 1H
DATA counts
1636CLK / 1H
CLK
55.5ns
*ns
*=Delay
V rate phase: Same as one in analog timing-chart
Digital output: Field ID signal superposed 1 line ahead of VS
FLD index pulse
G = 1H (Superposed on LSB)
1
st
FLD: H level output during data output (1636CLK)
2
nd
FLD: L level output during data output (1636CLK)
HD, VD Output Phase Lag
(1)Normal Mode (1
st
FLD, 2
nd
FLD), RTS Mode
No phase lag
CLK
DATA
HD
11
5CLK
1
636CLK
1
848CLK
*ns
97CLK
B
E
F
G
1
st field
2nd field
F.I
F.I
HD
VD
Summary of Contents for CS3920
Page 19: ...13 11 External view drawing ...