TELEREADER CWR-685E Service Manual Download Page 7

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2.3  Control of SW OUT REMOTE

The SW OUT REMOTE terminal of the rear panel is connected to the REMOTE (J3-4) terminal of
main PCB.

This  terminal  is  directly  shorted  by  the  contact  of  the  SEND-AUTO-RECEIVE  switch  when  this
switch is set to SEND side. When AUTO or RECEIVE position is selected, this terminal is controlled
by the TR9 on the main PCB.

This terminal and the SEND-AUTO-RECEIVE switch is so wired that the J8-5 on the main PCB may
be connected to GND when the switch is set to SEND position, and that the J8-8 is similarly con-
nected to GND when it is set to RECEIVE side. Thus, this terminal always monitors the state of this
switch, and controls the transmission and reception and TR9.

2.4  Flow of signal in transmission

When a key is depressed, an ASCII code of 8-bit parallel positive logic is delivered from the key-
board, and is given from pin 4 to pin 11 of J6 on the main PCB. In succession, a data strobe signal
of negative logic is applied to pin 13 of J6, and is converted to a pulse signal by the one-shot mul-
tivibrator in IC6 to be fed in pin 40 of IC32.

At this time, according to the initially set format, the IC32 set the IRQB (pin 37) to L level in order
to ask the MPU to read data. In consequence, the MPU, immediately or after finishing the process
being run at that time, reads the data from the keyboard being applied to PA0 to PA7 in IC32, and
returns the IRQB to H level at the same time, and delivers a data reading acknowledgement signal
to the CA2 (pin 39) as negative logic pulse signal of 1.183 µs. The ACK signal is not used when
feeding from the keyboard, but is used when controlling the system by means of other microcom-
puter or the like instead of the keyboard. In such a case, the parallel data should not be converted
until the response of ACK signal is confirmed.

When the MPU reads the data, a process suited to the state, such as command processing, writing
into transmission buffer area, writing into memory area, is effected according to the data.

REFERENCE

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In transmission of CW, the data in the transmission buffer is converted to CW code, and the
output  of  CW  output  port  (pin  2  of  IC27)  is  controlled  being  synchronized  with  the  clock
signal created in IC35 and read in from pin 2 of IC40. This clock frequency may be varied
by means of SPEED slide VR in the front panel.

When the CW output port becomes H level at TTL level, the TR5 and TR8 are turned on, so
that a key operation signal can be obtained from the SW OUT CW output terminal in the re-
ar panel connected to J3-6. In CW ID mode at the time of RTTY, the TR10 is turned off by
the signal of CW ID output port (pin 9 of IC27) which is operating simultaneously with CW
output port, and the signal is shifted to a blank space.

o

In transmission of RTTY, when the MPU writes data into USART, they are converted to serial
signals  in  synchronism  with  the  baud  rate  at  1/16  of  the  clock  given  to  pin  9  of  USART
(IC28),  and  are  delivered  from  TXD  (pin  19)  of  USART,  thereby  controlling  the  TTL-OUT
(J10-3 terminal) and TR10 as in the case of CW ID. The TTL-OUT (J10-3 terminal) of main
PCB is connected to the FSK (J6-2 terminal) on MODEM PCB, and is delivered at TTL level
to the FSK TTL OUT terminal in the rear panel from the FSK TTL (J4-9 terminal). The FSK
signal is, at the same time, applied also to pin 5 of IC4 as AFSK shift signal. The AFSK sig-
nal created here is delivered from J4-3 terminal on MODEM PCS, and is sent to the AFSK

Summary of Contents for CWR-685E

Page 1: ...CWR 685E SERVICE MANUAL Digitization and editing of text and images by DC7XJ August 2019...

Page 2: ...ng display 14 C Abnormal external display 15 4 2 Trouble of CRTC block 16 4 3 Trouble of computer block 19 4 4 Trouble in CW transmission 20 4 5 Trouble in CW reception 20 4 6 Trouble RTTY 21 5 Descri...

Page 3: ...ram 38 2 Keyboard circuit diagram 39 3 Built in CRT unit circuit diagram 40 4 Main PCB circuit diagram 5 MODEM PCB circuit diagram 6 General wiring diagram 7 Mechanism assembly drawing 11 Attached boo...

Page 4: ...re place the two ICs at the same time If specified tool cannot be used when dismounting remo ve with particular care not to bend the lead pins of ICs 4 In the description H level at TTL level or merel...

Page 5: ...directional data For selection of address there is an address data output terminal of 16 bits but since the A15 of higher position is not used in this system the total address space is 32 kbytes For c...

Page 6: ...d the key operation signal is given to a key signal input J3 2 and is read from the key sig nal input port pin 4 of IC45 to light up the LED for CW monitor thereby opening the output gate of CW monito...

Page 7: ...rolling the system by means of other microcom puter or the like instead of the keyboard In such a case the parallel data should not be converted until the response of ACK signal is confirmed When the...

Page 8: ...ile it is being depressed the J7 2 terminal on main PCB is connected to GND FILTER In OFF position the J7 3 terminal on main PCB is connected to GND In ON position the J7 4 terminal on main PCB is con...

Page 9: ...ontrol signal output ports This paragraph describes the performance of output ports on the main PCB in which outputs vary depending on the setting of each switch or commands These outputs are controll...

Page 10: ...3 3 Actions of CW audio demodulator The IC42 is a Norton amplifier having four logic circuits of identical function contained in one pack age In this system two of the four logic circuits are used to...

Page 11: ...y the output frequency of clock generator composed of IC35 TR1 TR2 The SPEED slide VR on the front panel is connected to the J9 8 to J9 10 terminals on main PCB When the voltage at J9 9 terminal is hi...

Page 12: ...eshooting Troubleshooting flow charts 4 1 Trouble of built in display A No display The built in display of this System appears in about ten seconds after the power switch is turned on If no display ap...

Page 13: ...he first place check the crystal oscillator and dividing circuit Trouble in CRTC block Check the frequency of the following parts in the numerical order checking of crystal oscillator di viding circui...

Page 14: ...w 12 V the performance of built in display becomes unstable 2 In the case of power source containing ripples the average voltage should not be more than 14 5 V If the display screen still fluctuates t...

Page 15: ...signal of 1 0 0 2 Vpp at 75 ohm load The sync signal level is 30 and video signal level 70 H SYNC 15 644 kHz pulse width 5 32 s V SYNC 59 26 Hz pulse width 2 1 ms Non interlaced raster scan system Num...

Page 16: ...16 4 2 Trouble of the CRTC block Is horizontal sync signal of about 63 92 s period delivered to CP1 and is vertical sync signal of about 16 875 ms period to CP2...

Page 17: ...17...

Page 18: ...18...

Page 19: ...the level is set to L for about 20 ms and is then set to H again e With the CW RTTY selector at RTTY when the SEND AUTO RECEIVE selector is set at SEND the switch is turned on and pin 14 of IC40 becom...

Page 20: ...e see the actions of external control signal output ports par 3 2 4 5 Trouble in CW reception When reception of CW is in trouble check if signal appears at check points of TP 5 TP 2 TP 4 While referri...

Page 21: ...signals are passed through a limi ter 1 4 IC3 and converted to signals stable in vertical direction The signals can be checked on TP 2 Then necessary frequency should be selected by the programmable...

Page 22: ...ogrammable divider is divided again to 1 2 and converted to a neces sary frequency of 50 duty One of the converted outputs is passed through audio amplifiers TR3 TR4 to become a monitor sound output w...

Page 23: ...by this divider is divided again to 1 2 and converted to a necessary frequency of 50 duty to delivered This output of baud rate clock can be checked on the TP 10 The relation between baud rate and cl...

Page 24: ...24 5 4 MODEM printed circuit board block diagram...

Page 25: ...R E from keyboard and set in echo back mode 6 Transmit RYRYRY from keyboard In this operation a self diagnosis loop is made In normal state Regardless of the selected position of RX TAPE selector on t...

Page 26: ...26...

Page 27: ...27...

Page 28: ...28 6 2 Modulator AFSK...

Page 29: ...29 6 3 Baud rate clock unit...

Page 30: ...30 7 Keyboard troubleshooting KB 685E KB 6850 7 1 Troubleshooting flow chart of keyboard PCB No 820226 1 Referring to the attached wiring diagram check the keyboard in connected state...

Page 31: ...31...

Page 32: ...B Q W E R T Y U I O P CR A S RS FS BS DLE DCI ETB ENQ DC2 DC4 EM NAK HT SI DLE NUL ESC CR SOH DC3 CAN CAN Q W E R T Y U I O P CR A S 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 5...

Page 33: ...same as 811001 0 but since the IC numbers and VR numbers differ refer to the wiring diagram The correspondence of VR numbers is as follows 801230 0 811001 1 Frequency VR 4 VR 5 VR 6 VR 7 VR 8 VR 9 VR...

Page 34: ...icked up For readjustment adjust the VRs by connecting oscilloscope to the TP 12 The relation between the baud rate frequency and time is as follows Baud rate Frequency f Hz Time T ms 45 5 50 57 56 92...

Page 35: ...CMOS LS TTL LS TTL LS TTL LS TTL LS TTL LS TTL PCI ROM ROM CPU PIA LS TTL LS TTL TIM LS TTL LS TTL LS TTL LS TTL LS TTL LS TTL OP AMP CMOS PLL LS TTL LS TTL REG REG R SW R Hi Hi Hi Hi Hi To Hi Hi Hi...

Page 36: ...Part No IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 IC15 IC16 IC17 IC18 IC19 IC20 IC21 TR1 TR2 TR3 TR4 D1 D4 D5 D6 D7 D8 D92 IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC I...

Page 37: ...IC13 IC14 IC15 IC16 IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC OP AMP OP AMP OP AMP CMOS OP AMP OP AMP TTL CMOS LS TTL LS TTL CMOS LS TTL M M M To M Hi To Hi Hi To LM339 or equivalent LM339 MC33...

Page 38: ...38 BLOCK DIAGRAM...

Page 39: ...39...

Page 40: ...40...

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