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2.2 Flow of signal
A block diagram is shown in attached sheet. Referring to the block diagram, the flow of signal is
explained below.
An audio signal fed from the AF IN (RX or TAPE) terminal of the rear panel when receiving is selec-
ted by the RX/TAPE input selector on the front panel, and is delivered to AF OUT terminal in the
rear panel, and is, at the same time, fed into AF input (J3-1) on MODEM PCB and AF input (J9-1)
on main PCB. Therefore, the AF OUT can be also used as AF input terminal (at this time, however,
the AF IN RX and AF IN TAPE must be used as output terminals).
The CW audio signal fed into the main PCB is given to the J9-3 for driving the AGC amplifier for
CW and input monitor Speaker, and, after being controlled in the volume by the input slide VR con-
nected between J9-3 and J9-5, drives the Speaker for input sound monitor connected between J9-
13 and J9-14 or the EXT SP output terminal.
The CW audio signal given to the AGC amplifier (IC42) passes through the active band pass filter
(IC42) at center frequency of 800 Hz, and is converted into a digital signal by the PLL System de-
coder (IC44) for CW to control the gate of monitor oscillation sound at 800 Hz for CW, and is si-
multaneously read from the CW signal input port (pin 2 of IC45) in the Computer block, thereby
flickering the LED for CW monitor at the same time.
When the CW/RTTY selector on the front panel is set at RTTY side, the CW/RTTY selection signal
input (J7-11) on the main PCB is at L level, and is read from the input port (pin 12 of IC40) in the
Computer block, and the gate (pin 1 of IC12) becomes L level at the same time. As a result, the
output of PLL decoder becomes invalid.
When a key on the keyboard which is connected to the telegraph terminal on the rear panel is
pressed, the key operation signal is given to a key signal input (J3-2), and is read from the key sig-
nal input port (pin 4 of IC45) to light up the LED for CW monitor, thereby opening the output gate
of CW monitor OSC. At the same time, transistor switches TR5, TR8 for keying-out (SW OUT CW)
are turned on.
At this time, the computer, in order to turn on the transistor switch TR9 for transmission and re-
ception control of the transmitter, sets the output port (pin 6 of IC27) to TTL level H, and sets the
reset delay timer, so that the signal may be set to the initial value again whenever key operations
are subsequently made. When the timer expires, the TR9 is cut off. Meanwhile, this timer is not
described in the circuit diagram because it is a software timer by the computer.
The CW signal read from the CW signal input port is decoded, and is delivered to the display
screen and printer.
The RTTY audio signal fed from J3-1 on MODEM PCB is converted into a digital signal (for details
of conversion see the description of performance of MODEM block), and is delivered from J4-7,
and is supplied to the INT side of the FSK DEMOD INT/EXT slide switch in the rear panel. At the
EXT side, a signal from the FSK TTL IN side is supplied. The digital signal selected by this slide
switch is fed again into the J4-8 of MODEM PCB.
The logic circuit composed of IC10, IC12 on the MODEM PCB selects either received demodulated
signal (TU/EXT) or sending signal (FSK) depending on the control signal STB or RX/TAPE given
from the main PCB, and delivers the selected signal to the FSK OUT (J6-3). The signal delivered
from the FSK OUT (J6-3) is fed into the FSK IN (J10-2) in the main PCB, and is given to RXD (pin
3) of RTTY received signal input port (IC28, USART), and is converted from serial to parallel in the
IC28 being synchronized with the baud rate of 1/16 of the clock applied to RXC (pin 25) of IC28.
The parallel data thus converted is decoded, and is delivered to the display screen and printer.
Summary of Contents for CWR-685E
Page 1: ...CWR 685E SERVICE MANUAL Digitization and editing of text and images by DC7XJ August 2019...
Page 17: ...17...
Page 18: ...18...
Page 24: ...24 5 4 MODEM printed circuit board block diagram...
Page 26: ...26...
Page 27: ...27...
Page 28: ...28 6 2 Modulator AFSK...
Page 29: ...29 6 3 Baud rate clock unit...
Page 31: ...31...
Page 38: ...38 BLOCK DIAGRAM...
Page 39: ...39...
Page 40: ...40...