Classification
Revision
Public
PA1
Document ID
Print date
19-2241
2019-05-02
buffer. After a set of buffers are completed user application has to reset data valid buffers by writing an
32-bit variable with value 1 in each position.
4.7
User Logic 2 Considerations
Metadata insertion and sample interleaving for two-channel mode is done in UL2. If UL2 is bypassed
GPU streaming will not work, writing to UL2 registers may alter functionality. If UL2 is modified with the
development kit, you have to make sure that metadata insertion still behaves correctly.
5
Example Code
The ADQ7 GPU P2P function is delivered with two examples, one for Nvidia GPU’s under Linux and
another for AMD GPU’s under Windows.
5.1
Signal Connections
The example code can collect data from one or two analog inputs using the A-trigger and optional B-
trigger as described in Section
. Table
shows how the different input signals are labeled on the
ADQ7 backplate.
Table 2: Signal connections for ADQ7 device
Signal
ADQ7 input
Analog channel A
A
Analog channel B
B (optional)
A-trigger
Trig
B-trigger
Sync (optional)
5.2
Nvidia Example
The example for Nvidia GPUs is written using GPUDirect with CUDA and OpenGL.
GPUDirect works by setting up a bus writable buffers in GPU memory. Additionally,
marker
buffers
are setup in host memory used to synchronize writes to the GPU buffers with host program execution.
When a GPU buffer has been completely written by the digitizer it writes an iterator to the associated
marker buffer in host and sends an interrupt. The host program waits for the marker write and enqueues
a CUDA kernel at that time. This sequence is repeated in an alternating pattern for two buffers.
The example uses a CUDA kernel which computes an FFT for each record in the buffer, and draws
a point to an OpenGL buffer indicating the peak frequency of the FFT. Fig.
shows a screen capture of
the CUDA example.
1
Nvidia and AMD are protected trademarks of their respective owners.
ADQ7 GPU Peer-To-Peer – User Guide
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