Tektronix SPG 1000, Instruction Manual

Page: 104 / 282

8–8
SPG 1000
Current mode control works by allowing the cur-
rent flowing in the primary to reach a peak level
that is set by the output of the error amp (internal
to U722), which is controlled by the +5 V output.
The current in the primary winding is sensed by
R630, and applied to U722-3 as a voltage. At the
start of the cycle the oscillator sets the flip-flop
within U722, which turns Q638 on. The primary
current, and therefore the voltage to U722-3,
ramps up until the I - SENSE level is sufficient to
trip the comparator. This resets the flip-flop, end-
ing the drive pulse to Q638, and the energy stored
in the transformer is transferred to the
secondaries.
Line regulation is accomplished automatically
without voltage feedback. As the input voltage
increases, the slope of the ramp increases, and the
trip point is reached sooner. This results in a
shorter pulse width. A decrease in line voltage
causes a decrease in the slope of the ramp, and it
takes longer to reach the trip point. The same
peak current is reached in both cases, however, so
the same amount of energy is transferred to the
load. Line regulation, then, is achieved before
variations in output voltage can occur.
Load regulation is accomplished by sensing the
output voltage of the + 5 V supply and comparing
it to a 2.5 V reference (internal to U410). U410 is
a band-gap reference set to function as an error
amp. Pin 3 of U410 is the error signal; this signal
is coupled to U722 through opto-isolator U520. If
the load increases, the signal at U722-2 drops in
Figure 8–4: Pulse Width Modulator and Error Amplifier Circuit