Tektronix P6910, Instruction Manual

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Reference
A processor also provides a good example of signals that can be useful as
quali
fi ers. There are often signals that indicate data reads versus data writes
(R/W), signals that show when alternate bus masters have control of the processor
buses (DMA), and signals that show when various memory devices are being
used (ChipSel). All of these signals are good candidates for assignment to
quali
fi er channels.
By logically AND'ing the clock with one of these quali fi ers you can program the
logic analyzer to store only data reads or data writes. Using the DMA signal as a
quali
fi er provides a means of fi ltering out alternate bus master cycles. Chip selects
can limit data latching to speci fi c memory banks, I/O ports, or peripheral devices.
Multiplexed buses
The logic analyzer can demultiplex data from multiplexed buses.
Each signal on a dual- or quad-multiplexed bus can be demultiplexed into its own
logic analyzer channel. Refer to the following tables to determine which channel
groups to connect to feed the test data to channels on the SUT.
Table 2: 2X demultiplexing source-to channel assignments
Prime channels receiving SUT test data
Base connecting channel groups
136-channel logic
analyzer 102-channel logic
analyzer 68-channel logic
analyzer 34-channel logic
analyzer
A3:7-0 D3:7-0 D3:7-0 C3:7-0 C3:7-0
A2:7-0 D2:7-0 D2:7-0 C2:7-0 C2:7-0
A1:7-0 D1:7-0 D1:7-0 D1:7-0
—
A0:7-0 D0:7-0 D0:7-0 D0:7-0
—
C3:7-0 C1:7-0 C1:7-0
— —
C2:7-0 C0:7-0 C0:7-0
— —
E3:7-0 E1:7-0
— — —
E2:7-0 E0:7-0
— — —
CLK:0 QUAL:1 QUAL:1
— —
CLK:1 QUAL:0 QUAL:0
— —
CLK:2 QUAL:3
— — —
CLK:3 QUAL:2
— — —
18 P6910 General Purpose Probe Instruction Manual