Theory of operation
This section describes the electrical operation of the AWG5200 Series Arbitrary Waveform Generators.
System overview
The AWG5200 Series Arbitrary Waveform Generators provide various models with different sample rates and numbers of channels.
System block diagram
The picture below is a basic block diagram for a single AWG5200 arbitrary waveform generator channel.
Stable timing is derived from a 10 MHz crystal oscillator. Alternatively, an external 10 MHz reference may be used. The 2.5-5.0 GHz clock
signal from the clock module is common to all AWG5200 channels. Each channel has independent clock timing (phase) adjustment which
is located on the DAC module.
The AWG FPGA waveform players are central to the design. These FPGAs retrieve waveform data from memory, receive clock and trigger
timing, and play out waveform data via an eight-lane high-speed-serial interface (JESD204B) to the DAC.
The DAC creates the waveform. The DAC output has four different paths: DC High Bandwidth (DC thru-path), DC High Voltage, AC direct
(AC thru-path), and AC amplified. Note that the AC signal is single-ended, and has its output at the positive-phase (CH+). The DC paths
are differential.
An AWG module contains two waveform players FPGAs. Each drives two DAC channels. A fully-loaded single AWG module provides
waveform data for four channels. Each DAC module has two channels.
Output bandwidth is a little less than half of the DAC sampling clock frequency. The DAC has a “double-data-rate” (DDR) mode where
the DAC is sampled at both rising and falling edges of the clock, and waveform values are interpolated on the falling-edge sample. This
doubles the image-suppressed bandwidth of the system.
Theory of operation
AWG5200 Series Arbitrary Waveform Generators Service Manual
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