Tekram Technology P5V30-B4, User Manual

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MAINBOARD BIOS SETUP MAINBOARD BIOS SETUP
P5V30-B4 User’s Manual P5V30-B4 User’s Manual
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DRAM Read Burst (EDO/FPM) - Sets the burst mode read timing for two different
DRAM types - (EDO/FPM). Burst read and write requests are generated by the CPU in four
separate parts. The first part provides the location within the DRAM where the read or
write is to take place, while the remaining three parts provide the actual data. The lower the
timing numbers, the faster the system will address memory. *
x222/x333 timings is the
default.
x222/x333 Read DRAM (EDO/FPM) timings are 2-2-2/3-3-3
x333/x444 Read DRAM (EDO/FPM) timings are 3-3-3/4-4-4
x444/x444 Read DRAM (EDO/FPM) timings are 4-4-4/4-4-4
DRAM Write Burst Timing - Sets the timing for burst mode writes from DRAM. Burst
read and write requests are generated by the CPU in four separate parts. The first part
provides the location within the DRAM where the read or write is to take place, while the
remaining three parts provide the actual data. The lower the timing numbers, the faster the
system will address memory. *
x333 timings is the default.
x222 Write DRAM timings are 2-2-2-2
x333 Write DRAM timings are 3-3-3-3
x444 Write DRAM timings are 4-4-4-4
DRAM RAS# Precharge Time - DRAM must continually be refreshed or it will lose its
data. Normally, DRAM is refreshed entirely as the result of a single request. This option
allows you to determine the number of CPU clocks allocated for the
R ow A ddress S trobe to
accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh
may be incomplete and data will be lost. Options are
3 or 4 Clocks. *Default = 3 CPU
Clocks .
DRAM R/W Leadoff Timing - Sets the number of CPU clocks allowed before reads and
writes to DRAM are performed. * 6 CPU Clocks is the default.
Fast RAS# to CAS# Delay - The DRAM row miss leadoff timing is controlled by this
option. This setup item allows you to determine the timing of the transition from Row
Address Strobe (RAS) to Column Address Strobe (CAS). Options are
2 or 3 Clocks delay.
* 3 CPU clocks is the default.
Fast MA to RAS# Delay -
This setup item allows you to determine the timing of the
transition from MA (low Memory Address) ready to RAS activated. Options are 1 or 2
Clocks delay. * 1 CPU clocks is the default.
Fast EDO Path Select - When Enabled , a fast path is selected for CPU to DRAM read
cycles for the leadoff. This results in a 1 HCLK pull-in for all read leadoff latencies for