Teknor Industrial Computers VIPer 821, Technical Reference Manual

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BIOS Setup Program
4-7
Option BIOS
Default
Setup
Default
Possible
Settings
Description
Peer Concurrency En. En. En., Dis. Peer concurrency means that more than one PCI device can be
active at a time.
Chipset Special
Features En. En. En., Dis. When Disabled, the chipset behaves as if it were the earlier Intel
82430FX chipset.
DRAM ECC/PARITY
Select Parity Parity ECC, Parity Set this option according to the type of DRAM installed in your
system: error-correcting code (ECC) or parity (default).
Memory Parity/ECC
Check Auto Auto En., Dis., Auto In Auto mode, the BIOS enables memory checking automatically
when it detects the presence of ECC or parity DRAM.
Single Bit Error Report En. En. En., Dis. If ECC is enabled, selecting Enabled here tells the system to
report an error when a correctable single-bit error occurs.
Chipset NA# Asserted En. En. En., Dis. When Enabled, the chipset will use the NA (Next Address)
protocol with the CPU to enable cache bursting.
Pipeline Cache Timing Faster Faster Faster,
Fastest
For a secondary cache of 256KB (one bank), select Faster. For a
secondary cache of 512KB (two banks), the system designer must
select Faster (3-1-1-1, 2-1-1-1) or Fastest (3-1-1-1, 1-1-1-1).
Cache timing 3-1-1-1 is at the CPU access speed. It requires
special SRAMs because the 3-1-1-1 timing is at the CPU clock
rate.
Passive Release En. En. En., Dis. When Enabled, CPU to PCI bus accesses are allowed during
passive release otherwise the arbiter only accepts another PCI
master access to local DRAM.
Delayed Transaction Dis. En. En., Dis. The chipset has an embedded 32-bit posted write buffer to
support delay transactions cycles. Select Enabled to support
compliance with PCI specifications version 2.1.
Memory Hole Location None None 512K-640K,
15M-16M,
None
You can reserve this area of system memory for ISA adapter
ROM. W hen this area is reserved, it cannot be cached. The user
information of peripherals that need to use this area of system
memory usually discusses their memory requirements.
Supervisor I/O Base
Addr. 190h 190h 190h, 290h,
390h
This option determines the base address for the Supervisor I/O
Register.