Teknor Industrial Computers TEK-CPCI 1003, Technical Reference Manual, Page: 59 / 122

11-1
11. CPCI I/O SIGNALS
This section describes integrated feature signals available on rear panel CPCI I/O
connectors (J3, J4, and J5).
11.1 J3 SIGNAL SPECIFICATION
11.1.1 V-PORT
Signal Pin Assignation (J3) Description
VP-OUT A1 Reserved
ZVPCLK B1 V-Port clock from the video source pixel clock
VP-IN C1 Reserved
VACTI D1 Video (data) Active Input
VSCL2 B2 I2C clock
VP 0-7 A5, C5, E5, B4, D4, A3,
C3, E3 V-Port pixel data
VSDA2 A4 I2C data
/VP-HSYNC C4 Horizontal Synch.
/VP-VSYNC D2 Vertical Synch.
/EN-CAM E4 Enable camera
11.1.2 Ethernet LEDS
Signal Pin Assignation (J3) Description
SPEEDLED 0-1
A6, E6 Speed LED signal
LINKLED 0-1
B6, D6 Link integrity LED signal
ACTLED 0-1
C6, A7 Transmit / receive activity LED signal
11.1.3 Ethernet 1
Signal Pin Assignation (J3) Description
ETX+1 A9 Ethernet 1 High Transmit Data line
ETX-1 B9 Ethernet 1 Low Transmit Data line
ERX+1 C9 Ethernet 1 High Receive Data line
ERX-1 D9 Ethernet 1 Low Receive Data line