Teknor Industrial Computers PCI-934, Technical Reference Manual

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BIOS Setups
13-7
13.5 CHIPSET FEATURES SETUP
Option BIOS
Default
Setup
Default
Possible
Settings
Description
Auto Configuration En. En. En. ; Dis. Auto Configuration selects predetermined optimal values of chipset
parameters. When Disabled, chipset parameters revert to setup
information stored in CMOS. Many fields in this screen are not
available when Auto Configuration is Enabled.
DRAM Timing 70 ns 70ns 70 ns, 60ns The value in this field depends on performance parameters of the
installed memory chips (DRAM). Do not change the value from the
factory setting unless you install new memory that has a different
performance rating than the original DRAMs.
DRAM RAS
#
Precharge Time
4 4 4 ; 3 Select the number of CPU clocks allocated for the Row Address
Strobe (RAS
#
) signal to accumulate its charge before the DRAM is
refreshed. If insufficient time is allowed, refresh may be incomplete
and data lost.
DRAM R/W Leadoff
Timing
7/6 7/6 7/6 ; 6/5
Select the combination of CPU clocks the DRAM on your board
requires before each read from or write to the memory. Changing the
value from the setting determined by the board designer for the
installed DRAM may cause memory errors.
Fast RAS# to CAS#
Delay 3 3 3 ; 2 When DRAM is refreshed, both rows and columns are addressed
separately. Use this item to determine the transition timing from RAS
to Column Address Strobe (CAS).
DRAM Read Burst
(EDO/FPM) x444/x
444
x444/x
444
x444/x444 ;
x333/x444 ;
x222/x333
Sets the timing for reads from EDO (Extended Data Output) or FPM
(Fast Page Mode) memory. The lower the timing numbers, the faster
the system addresses memory. Selecting timing numbers lower than
the installed DRAM is able to support can result in memory errors.
DRAM Write Burst
Timing x444 x444 x444 ; x333 ;
x222
Sets the timing for writes to memory. The lower the timing numbers,
the faster the system addresses memory. Selecting timing numbers
lower than the installed DRAM is able to support can result in
memory errors.
Turbo Read Leadoff Dis. Dis. En. ; Dis. Select Enabled to shorten the leadoff cycles and optimize
performance in cacheless, 50-60 MHz, or one-bank EDO DRAM
systems.
DRAM Speculative
Leadoff Dis. Dis. En. ; Dis. A read request from the CPU to the DRAM controller includes the
memory address of the desired data. When Enabled, Speculative
Leadoff lets the DRAM controller pass the read command to memory
sightly before it has fully decoded the address, thus speeding up the
read process.
Turn-Around Insertion Dis. Dis. En. ; Dis. When Enabled, the chipset inserts one extra clock to the turn-around
of back-to-back DRAM cycles.
ISA Clock PCI
CLK/4
PCI
CLK/4
PCICLK/4 ;
PCICLK/3
You can set the speed of the AT bus at one-third or one-fourth of the
CPU clock speed.
System BIOS
Cacheable Dis. En. En., Dis. Selecting Enabled allows caching of the system BIOS ROM at
E0000h-FFFFFh, resulting in better system performance. However,
if any program writes to this memory area, a system error may occur.
Video BIOS Cacheable Dis. En. En., Dis. Selecting Enabled allows caching of the video BIOS ROM at C0000h
to C8FFFh, resulting in better video performance. However, in any
program writes to this memory area, a system error may occur.
8 Bit I/O Recovery
Time 3 1 1 ; 2 ; 3 ; 4 ; 5 ;
6 ; 7 ; 8 ; NA
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place because
the PCI bus is so much faster than the ISA bus. These two fields let
you add recovery time (in bus clock cycles) for 16-bit and 8-bit I/O.
16 Bit I/O Recovery
Time 2 1 1 ; 2 ; 3 ; 4 ;
NA
...