Te chnologic Sys t e ms
Da t e
Tit le :
Re v:
De s igne r
She e t
of
3
TS-7558 RAM, RTC, Fla s h, SD ca rd
DDR1 SDRAM
I2C bus
RTC
The DDR clock diffe re nt ia l pa ir is t he mos t crit ica l t ra ce on t he e nt ire boa rd
The da t a line s in e a ch byt e la ne ca n be s wa ppe d on t he RAM chip for opt ima l la yout
The t ra ce le ngt h of e a ch da t a line (in a s ingle byt e la ne ) a nd t he re s pe ct ive
QS a nd DM s igna ls mus t be ma t che d t o wit hin 2. 5 mm
Addre s s a nd Comma nd s igna ls ca n be groupe d t oge t he r, but mus t be is ola t e d
from da t a a nd M_DSQ a nd M_DM s igna ls (by a t le a s t . 5 mm)
Or run t he m on diffe re nt la ye r
Exa mple : D0 a nd D5 ca n be s wa ppe d, but not D7 a nd D8
DDR RAM Not e s
NAND Fla s h
512 Mbyt e
64 Mbyt e
Micro SD Ca rd Socke t
RN4 is 4. 7K !
12
A
Ma y 20, 2011
(I2C)
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