Te chnologic Sys t e ms
Da t e
Tit le :
Re v:
De s igne r
She e t
of
TS-7558 FPGA, JTAG He a de r
2
Pull-up a nd pull-down re s is t ors
a re 6 t o 30K ohms
Se t CONFIG_MODE t o NONE
This a llows a ll pins t o be us e d
XP2-5 ha s :
9 blocks of 1Kx18 Block RAM
12 18x18 Mult iplie rs
5K LUTS 2 PLLs
100 I/ O wit h 144 pin pa cka ge
"ins t a nt ON" = a bout 1. 5 mS
input PLL clock = 10 MHz min
Powe r Supplie s ca n be s e que nce d in a ny orde r
All I/ O line s a re t ri-s t a t e d during powe r cycling
but mus t be monot onic
Pa ge 37 of Da t a She e t (Hot Socke t ing)
FPGA wit h 5000 LUTs
Int e rrupt s
I2C
SPI_CS0#
I2S
SPI_CS1#
LED0
LED1
RLM
Cons ole a lwa ys is e na ble d
MODE1 a nd MODE2 s t a t e s
a re la t che d whe n
CPU_RESET# is de a s s e rt e d
MODE1 a nd MODE2
ha ve 4. 7K re s is t or
pull-ups on WM-7550
JTAG
He a de r
26-pin
Mode 1
Mode 2
Boot s from
1
1
NAND Fla s h
0
1
SD Ca rd
1
0
0
0
Off-boa rd Fla s h
Off-boa rd Fla s h
Us e 680 ohm re s is t or
t o GND t o s e t low
Pin 54
Pin 138
(we a k PD)
(we a k PU)
TS-7500
TS-7550
WM-7551
TS-7552
TS-4500
1
1
1
1
0
0
1
0
Pin 71
0
7552 a nd 7553 FPGA pin 93 = MISO
Pin 37
1
1
1
1
0
0
0
1
1
1
0
Boa rd ID bit s
TS-7553
1
0
1
0
TS-7554
0
0
1
0
TS-7558
0
1
1
0
He x
F
B
C
D
9
8
A
0
Ma y 20, 2011
12
A
139 mus t be
bia s e d high
FPGA pin
