10 Watchdog Timer
Table 10a Watchdog Timeout Register
Value (Hex) MSB MID LSB
Timeout Period
00
0
0
0
Watchdog Disabled
01
0
0
1
250 mS
02
0
1
0
500 mS
03
0
1
1
1 second
04
1
0
0
-- Reserved
05
1
0
1
2 seconds
06
1
1
0
4 seconds
07
1
1
1
8 seconds
The TS-7200 implements a watchdog
timer (WDT) unit in the Xilinx PLD. The
WDT can be used to prevent a system
“hanging” due to a software failure. The
WDT causes a full system reset when
the WDT times out, allowing a
guaranteed recovery time from a
software error. To prevent a WDT
timeout, the application must
periodically “feed” the WDT by writing a
specific value to a specific memory
location.
The WDT Control register must be
initialized with the timeout period desired. This may be as short as 250 mS or may be as
high as 8 seconds. After the WDT has been enabled, the WDT counter starts counting.
The application software can reset this counter at any time by “Feeding the WDT”. If the
WDT counter reaches the timeout period, then a full system reset occurs.
Table 10b Watchdog Control Registers
Register
Address
Access
WDT Control register 0x2380_0000 Read/Write
WDT Feed register
0x23C0_0000 Write Only
In order to load the WDT Control register,
the WDT must first be “fed”, and then
within 30 uS, the WDT control register
must be written. Writes to this register
without first doing a “WDT feed”, have no
effect.
In order to clear the WDT counter (feeding the watchdog), a value of 05 must be written
to the WDT Feed register.
Warning!
Do not attempt to use the Watchdog Timer in the EP9302.
When using the Linux OS, the watchdog can be reached from user C code by using the
mmap() system call on the /dev/mem special file to map the areas of physical address
space into process user address space. A user process does not have the physical
address space of the watchdog registers mapped by default.
TS-7200 User's Manual
Technologic Systems
http://www.embeddedARM.com/
25
12/2004
Summary of Contents for TS-7200
Page 1: ...TS 7200 User s Manual...