2/11/2020
TS-7100 - Technologic Systems Manuals
https://wiki.embeddedarm.com/w/index.php?title=TS-7100&printable=yes
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Chip
Pin
Location
6
13
DIO 3 Out or PWM on CN32 Terminal
6
14
HSPWM enable
6
15
PWM enable, both OE and dat
7
0
7
2
FPGA Strapping Pin
7
3
FPGA Strapping Pin
7
4
FPGA Strapping Pin
7
5
FPGA Strapping Pin
7
6
Data 0: Select 3.3 V power on CN16 XBee Socket
Data 1: Select 4 V power on CN16 XBee Socket
7
8
Enable MODEM on CN16 XBee Socket
7
9
Enable USB interface on CN16 XBee Socket
7
10
I/O over-current/over-voltage breaker tripped
7
11
FPGA Strapping Pin
7
12
FPGA Strapping Pin
7
13
Reserved
7
14
LCD backlight enable
1.
↑
This bit is read only. Clearing the associated current loop enable bit will set this bit, setting the
CL enable will clear this bit
2.
↑
To disable power on this pin, set the GPIO as an input with 'gpioset' or otherwise
3.
4.
This will relocate the USB channel connected to the top USB host port
5.
This bit must be cleared manually after a trip to de-assert the associated IRQ
10.6.1 Digital Inputs
The digital inputs on the TS-7100-Z are capable of supporting various voltage ranges and input modes. The digital
inputs support dry contact switches as well as a driven input voltage. The table below lists each digital input, the
bank and pin number for reading the input, the maximum input voltage range, the threshold voltages, as well as the
location of the input. VIH Min is the minimum voltage on the input to trigger a logic 1 input. VIL Max is the
maximum voltage on the input to trigger a logic 0 input. All of the digital inputs are hysteretic. The driving input
must be able to at least sink current to drive the input low, but all digital inputs are compatible with push-pull
drivers.
