FLEX-IMX8M-Mini HARDWARE MANUAL
– VER 1.00 – JAN 31 2020
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5.3. MIPI Camera
This section introduces the MIPI CSI-2 RX subsystem with the CSI-2 RX PHY and host
controller. This subsystem handles the sensor/image input and process for all the input
imaging devices.
The MIPI-CSI2 Controller has the following key features:
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Implements all three CSI-2 MIPI layers (Pixel to byte packing, low level protocol,
•
Lane management)
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Supports unidirectional Master operation
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Transmitter and receiver versions
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Scalable data lane support, 1 to 4 Data Lanes
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Supports high speed mode(80Mbps - 1.5Gbps) per lane, providing 4K@30fps capability for
the 4 lanes
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Supports 10Mbps data rate in low power mode
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Includes high speed deserializers
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Loopback testability support
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Support for all CSI-2 data types
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Virtual Channel support
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Support for DPHY Ultra Low Power State (ULPS)
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Error collection support (Rx Only)
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Flexible pixel-based user interface
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Supports user generated packets
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Supports single, double, or quad pixel interface
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Supports PHY Protocol Interface (PPI) compatible MIPI D-PHYs
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Delivered fully integrate and verified with target MIPI D-PHY
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RX Video Interface
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APB Control and Status Register (CSR) interface with IRQ support
For additional details, please refer to the “MIPI CSI Host Controller (MIPI_CSI)” chapter of the
“i.MX8M Mini Applications Processor Reference Manual”.
