TechNexion EDM1-IMX6, Manual

Page: 67 / 80

EDM1-IMX6 HARDWARE MANUAL
– VER 1.00 – NOV 14 2019
Page 67 of 80
EDM
PIN
i.MX6
BALL
PAD NAME Signal V I/O Description
73 H20 EIM_D21 I2C1_SCL 5V I/O
Display ID DDC data line
used for HDMI detection. If
not used this can be assigned
to General Purpose I
2
C bus
clock line
74 N20 DI0_PIN3 IPU1_DI0_PIN03 3V3 O LCD Vertical Synchronization
75 G23 EIM_D28 I2C1_SDA 5V I/O
Display ID DDC data line
used for HDMI detection. If
not used this can be assigned
to General Purpose I
2
C bus
data line
76 P25 DI0_PIN4 IPU1_DI0_PIN04 3V3 O LCD backlight enable/disable
77 GND GND P Ground
78 N21 DI0_PIN15 IPU1_DI0_PIN15 3V3 O LCD dot enable pin signal
79 NC Not Connected
80 A20 SD4_DAT3 GPIO2_IO11 3V3 O LCD Voltage On
81 NC Not Connected
82 F17 SD4_DAT2 PWM4_OUT 3V3 O
LCD Backlight brightness
Control
83 GND GND P Ground
84 RSVD Reserved
85 D7 CLK1_P XTALOSC_CLK1_P 2V5 O
PCI Express channel A clock
differential pair positive signal
86 F15 NANDF_CS0 NAND_CE0_B 3V3 O GPMC Chip Select bit A
87 C7 CLK1_N XTALOSC_CLK1_N 2V5 O
PCI Express channel A clock
differential pair negative
signal
88 GND GND P Ground
89 GND GND P Ground
90 C16 NANDF_CS1 NAND_CE1_B 3V3 O GPMC Chip Select bit B
91 B3 PCIE_TXP PCIE_TX_P 2V5 O
PCI Express channel A
Transmit output differential
pair positive signal
92 A17 NANDF_CS2 NAND_CE2_B 3V3 O GPMC Chip Select bit C
93 A3 PCIE_TXM PCIE_TX_N 2V5 O
PCI Express channel A
Transmit output differential
pair negative signal
94 GND GND P Ground
95 GND GND P Ground
96 D16 NANDF_CS3 NAND_CE3_B 3V3 O GPMC Chip Select bit D
97 B2 PCIE_RXP PCIE_RX_P 2V5 I
PCI Express channel A
Receive input differential pair
positive signal
98 NC Not Connected
99 B1 PCIE_RXM PCIE_RX_N 2V5 I
PCI Express channel A
Receive input differential pair
negative signal
100 GND GND P Ground