Teac TFT IDTV, Service Manual

Page: 25 / 78

21
22” TFT TV Service Manual 13/10/2004
pulses during the vertical interval. The COAST signal is generally
not
required for
PC-generated signals. The logic sense of this pin is controlled by Coast Polarity
(register 0FH, Bit 3). When not used, this pin may be grounded and Coast Polarity
programmed to 1, or tied HIGH (to VD through a 10 k resistor) and Coast Polarity
programmed to 0. Coast Polarity defaults to 1 at power-up.
REF BYPASS Internal Reference BYPASS
Bypass for the internal 1.25 V band gap reference. It should be connected to
ground through a 0.1 µF capacitor. The absolute accuracy of this reference is ±4%,
and the temperature coefficient is ±50 ppm, which is adequate for most AD9883A
applications. If higher accuracy is required, an external reference may be
employed instead.
MIDSCV Midscale Voltage Reference BYPASS
Bypass for the internal midscale voltage reference. It should be connected to
ground through a 0.1 µF capacitor. The exact voltage varies with the gain setting of
the BLUE channel.
FILT External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter.
Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize
noise and parasitics on this node.
POWER SUPPLY
V
D
Main Power Supply
These pins supply power to the main elements of the circuit. They should be as
quiet and filtered as possible.
V
DD
Digital Output Power Supply
A large number of output pins (up to 25) switching at high speed (up to 110 MHz)
generate a lot of power supply transients (noise). These supply pins are identified
separately from the VD pins so special care can be taken to minimize output noise
transferred into the sensitive analog circuitry. If the AD9883A is interfacing with
lower voltage logic, VDD may be connected to a lower supply voltage (as low as
2.5 V) for compatibility.
V
D
Clock Generator Power Supply
The most sensitive portion of the AD9883A is the clock generation circuitry. These
pins provide power to the clock PLL and help the user design for optimal
performance. The designer should provide “quiet,” noise-free power to these pins.
GND
Ground
The ground return for all circuitry on chip. It is recommended that the AD9883A be
assembled on a single solid ground plane, with careful attention to ground current
paths.