Teac 11AK33, Service Manual

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14
Features
General
n Feature selection via special function register
n Simultaneous reception of TTX, VPS, PDC, and WSS (line 23)
n Supply Voltage 2.5 and 3.3 V
n ROM version package P-SDIP 52, P-MQFP64
n Romless version package P-MQFP100,P-LCC84
External Crystal and Programmable clock speed
n Single external 6MHz crystal, all necessary clocks are generated internally
n CPU clock speed selectable via special function registers.
n Normal Mode 33.33 Mhz CPU clock, Power Save mode 8.33 Mhz
Microcontroller Features
n 8bit 8051 instruction set compatible CPU.
n 33.33-MHz internal clock (max.)
n 0.36 0 ms (min.) instruction cycle
n Two 16-bit timers
n Watchdog timer
n Capture compare timer for infrared remote control decoding
n Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)
n ADC (4 channels, 8 bit)
n UART
Memory
n Non-multiplexed 8-bit data and 16 20-bit address bus (ROMless Version)
n Memory banking up to 1Mbyte (Romless version)
n Up to 128 Kilobyte on Chip Program ROM
n Eight 16-bit data pointer registers (DPTR)
n 256-bytes on-chip Processor Internal RAM (IRAM)
n 128bytes extended stack memory.
n Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX
n UP to 16KByte on Chip Extended RAM(XRAM) consisting of;
- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX)
- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software
- 3 Kilobyte Display Memory
Display Features
n ROM Character Set Supports all East and West European Languages in single device
n Mosaic Graphic Character Set
n Parallel Display Attributes
n Single/Double Width/Height of Characters
n Variable Flash Rate
n Programmable Screen Size (25 Rows x 33...64 Columns)
n Flexible Character Matrixes (HxV) 12 x 9...16
n Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical
Redefinable Characters in Enhanced Mode
n CLUT with up to 4096 color combinations
n Up to 16 Colors per DRCS Character
n One out of Eight Colors for Foreground and Background Colors for 1-bit DRCS and ROM Characters
n Shadowing
n Contrast Reduction
n Pixel by Pixel Shiftable Cursor With up to 4 Different Colors
n Support of Progressive Scan and 100 Hz.
n 3 X 4Bits RGB-DACs On-Chip
n Free Programmable Pixel Clock from 10 MHZ to 32MHz
n Pixel Clock Independent from CPU Clock
n Multinorm H/V-Display Synchronization in Master or Slave Mode
Acquisition Features
n Multistandard Digital Data Slicer
n Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)
n Four Different Framing Codes Available
n Data Caption only Limited by available Memory
n Programmable VBI-buffer
n Full Channel Data Slicing Supported
n Fully Digital Signal Processing
n Noise Measurement and Controlled Noise Compensation
n Attenuation Measurement and Compensation
n Group Delay Measurement and Compensation
n Exact Decoding of Echo Disturbed Signals
Ports
n One 8-bit I/O-port with open drain output and optional I
2
C Bus emulation support(Port0)
n Two 8-bit multifunction I/O-ports (Port1, Port3)
n One 4-bit port working as digital or analog inputs for the ADC (Port2)
n One 2-bit I/O port with secondary functions (P4.2, 4.3, 4.7)
n One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)